tag:blogger.com,1999:blog-19092890.post2945602279804734746..comments2024-03-28T17:41:43.970+02:00Comments on Image Sensors World: Albert Theuwissen Reviews ISSCC 2019 - Part 2Vladimir Koifmanhttp://www.blogger.com/profile/01800020176563544699noreply@blogger.comBlogger14125tag:blogger.com,1999:blog-19092890.post-17425561777406931882019-03-09T21:46:00.033+02:002019-03-09T21:46:00.033+02:00Care to share INL & DNL figures ?Care to share INL & DNL figures ?Unknownhttps://www.blogger.com/profile/00061406865121843176noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-78173136741984123032019-03-09T18:48:21.655+02:002019-03-09T18:48:21.655+02:00So, what happens when the time form the comparator...So, what happens when the time form the comparator switching is very close to the clock edge, almost simultaneously? How do you decide what is THIS clock edge and what is the NEXT one?Vladimir Koifmanhttps://www.blogger.com/profile/01800020176563544699noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-6000504798700212332019-03-09T17:13:06.677+02:002019-03-09T17:13:06.677+02:00Both INL and DNL are shown. Both INL and DNL are shown. Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-19092890.post-90428822239089585302019-03-09T17:11:24.587+02:002019-03-09T17:11:24.587+02:00Both INL and DNL are shown. The issue of metastabi...Both INL and DNL are shown. The issue of metastability is solved by measuring the time difference between the comparator output and NEXT clock edge of the counter. Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-19092890.post-37843417457917564682019-02-22T15:42:30.651+02:002019-02-22T15:42:30.651+02:00The faster the clock, the harder it must be to con...The faster the clock, the harder it must be to control inaccuracies due to rise/fall time, comparator speed etc ... . You may get some missing codes.Unknownhttps://www.blogger.com/profile/00061406865121843176noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-50579189390444306932019-02-22T12:22:37.122+02:002019-02-22T12:22:37.122+02:00In the talk the authors mentioned that 6+4 is the ...In the talk the authors mentioned that 6+4 is the optimum (in the case of a 10-bit). It is not only the number of clocks, but also the clocking frequency that counts.Albert Theuwissen - Harvest Imagingnoreply@blogger.comtag:blogger.com,1999:blog-19092890.post-46740070757626242172019-02-22T10:52:04.834+02:002019-02-22T10:52:04.834+02:00Not that I know of. They also did not address the ...Not that I know of. They also did not address the issues of metastability or ambiguity. For example, what happens if MSB comparator changes at exactly clock edge - the MSB counter might count this as "1" while LSB logic might see it as "0" in that clock cycle.Vladimir Koifmanhttps://www.blogger.com/profile/01800020176563544699noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-56274675125346147522019-02-22T10:34:56.957+02:002019-02-22T10:34:56.957+02:00That would be interesting to have INL & DNL FO...That would be interesting to have INL & DNL FOM. Did the authors communicate on that ?Unknownhttps://www.blogger.com/profile/00061406865121843176noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-4839405649966857152019-02-22T09:54:01.939+02:002019-02-22T09:54:01.939+02:00I'd guess the limiting factor is the time stre...I'd guess the limiting factor is the time stretcher inaccuracies, controls rise/fall time, and column-to-column variations. If not that, one could build a hierarchical chain of time stretchers and add another 5b to resolution.Vladimir Koifmanhttps://www.blogger.com/profile/01800020176563544699noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-32030558688902906022019-02-22T00:14:37.232+02:002019-02-22T00:14:37.232+02:00Why not 5bit+5bit combination instread of 6bit+4bi...Why not 5bit+5bit combination instread of 6bit+4bit in the second paper?<br />Total clock cycles will be further reduced to 64 instead of 80. Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-19092890.post-18670195130272318902019-02-21T13:36:12.529+02:002019-02-21T13:36:12.529+02:00I've added a slide explaining the time stretch...I've added a slide explaining the time stretcher concept.Vladimir Koifmanhttps://www.blogger.com/profile/01800020176563544699noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-59317707871514202812019-02-21T13:02:24.063+02:002019-02-21T13:02:24.063+02:00I guess that time stretcher is a clock multiplier ...I guess that time stretcher is a clock multiplier circuit like a PLL/DLLAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-19092890.post-22842641368222872182019-02-21T11:58:34.597+02:002019-02-21T11:58:34.597+02:00I wonder about the time stretcher amp. Did they gi...I wonder about the time stretcher amp. Did they give details about it ?Unknownhttps://www.blogger.com/profile/00061406865121843176noreply@blogger.comtag:blogger.com,1999:blog-19092890.post-78589989259665276282019-02-21T11:30:53.121+02:002019-02-21T11:30:53.121+02:00the time-stretched SS-ADC is a very interesting id...the time-stretched SS-ADC is a very interesting idea! Congrats to Prof. Chae and his team! Anonymousnoreply@blogger.com