CEA-Leti and EPFL pre-announces its paper on fast and low noise image sensor based on thin-oxide pmos SF, to be published in September issue of JSSC:
A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process
Boukhayma, Assim; Enz, Christian; Peizerat, Arnaud
Abstract:
A sub-0.5e−rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5μA the sensor chip features an input-referred noise histogram from 0.25 e−rms to a few e−rms peaking at 0.48 e−rms. The imager features a full well capacity of 6400 e− and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6e-/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode.
How can a pinned photodiode be achieved in a standard CMOS process? the word standard here is somewhat misleading...
ReplyDeleteWell of course, you need to add a few implants, but it's quite possible to take a standard logic process and from a PPD.
ReplyDeletewhat would be the read noise at 80fps?
ReplyDeleteThe noise is measured at 80 fps. Each pixel is read in 25 us.
DeleteWhat is the expected QE of this sensor ?
ReplyDeleteThe fill factor of the 6.5 um pitch pixel is 40% and the effective measured QE is 32%. So the active area of the pixel (PPD) has a QE of 80% at about 500 nm. So a larger version of the pixel with higher fill factor will improve the QE using the same readout circuit technique.
DeleteOK.
DeleteIs it a front or a back illuminated sensor ?
FSI
DeleteI guess it could be interesting to try to develop a BSI version of this sensor : better fill factor, higher QE, maybe lower dark current and same ultra low readout noise ? And further trying to increase number of pixels.
DeleteI have in mind the GSENSE 400 BSI VIS sensor.
Thanks for the answers.
This sounds very interesting! We are following up this work at EPFL and we have ideas to further decrease the noise, so if you are interested in an academical partnership don't hesitate to contact us at ICLAB: https://people.epfl.ch/assim.boukhayma.
Deletewow, seems like the first "usable" (decent resolution and FWC) sensor with sub-0.5e noise
ReplyDeleteWhich temperature for the dark current?
ReplyDeleteRoom temperature
DeleteAren't industry DC measurements quoted at 60C (junction temperature) not room temperature (junction + ambient)?
DeleteI expect the upcoming JSSC paper will be related to this recent, open-access paper in our Sensors Special Issue on Photon Counting Image Sensors:
ReplyDeletehttp://www.mdpi.com/1424-8220/16/4/514
Also see this paper from a year ago at IISW:
ReplyDeleteA 0.4 e-rms Temporal Readout Noise, 7.5 μm pitch and a 66% fill factor Pixel for Low Light CMOS Image Sensors
Assim Boukhayma1,2, Arnaud Peizerat1 and Christian Enz2
1CEA-LETI, Grenoble, France ; 2ICLAB, EPFL, Switzerland
http://www.imagesensors.org/Past%20Workshops/2015%20Workshop/2015%20Papers/Sessions/Session_12/12-03_Boukhayama-peizerat.pdf
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ReplyDeleteThis paper will be published as an open-access article in IEEE xlplore. An early access version will be available before September.
ReplyDeleteAssim,
Deleteif the new pixel is related to the previous work, then is the following true?
1. Pixel gain = ~185uV/e-
2. Pixel voltage range = ~1.5V
3. Get the lowest noise, a column gain of 64 is employed.
if yes, does this then mean that the full well of the pixel is ~1.5V / 185uV = ~8000e-
and to get the low noise, the conversion gain is increased by 64X thus lowing the visible full well to only ~130e-???
in other words, when the chip is operating in it's high performance .4e- rms noise, it has a dynamic range of 130:1 or ~7bits?
thanks.
It is not exactly the same pixel but indeed, Pixel gain = ~160uV/e-, the pixel voltage range slightly higher than 1V and the full well is 6400e-.
DeleteThe problem of low dynamic at high gain is known and has already been solved in the literature. For instance (The CIS presented by Fairchild in IISW2011):
http://www.imagesensors.org/Past%20Workshops/2011%20Workshop/2011%20Papers/P35_Fowler_HDR.pdf
the idea was to read with both gains (two parallel column amplifiers) and chose one of the two values with post processing.
Further decreasing the noise at the high gain mode to reach deep subelectron levels using only the degrees of freedom left to the designers without process refinements and without having to increase dramatically the pixel CG or reduce its FWC was the main challenge of this work.
Wow! This is a real 0.5e- noise image sensor. Other approaches (not talking about QIS etc.) presented by people are impossible to implement in reality and are only for fiction lovers.
ReplyDeleteHi Assim, I read your paper. Very nice work!
ReplyDeleteIn a figure you show that using a high column amplification of 64x you reduce the noise from 20e (thermal noise limited) to 0.5e (1/f noise limited). Is this a spelling error? Otherwise this would suggest that you are not thermal noise limited at low gain but rather ADC, or other stage readout noise. In case of thermal noise limitation, you should see the noise reduce as the sqrt of the gain reaching 2.5e (20e/sqrt(64)=2.5). What I mean here is that most probably you can get an even lower noise than the 0.5e just by improving the noise performance of the successive stages.
Hi Adi, In fact the readout chain is not thermal noise limited at a column gain of 1. In fact with no column level gain, the noise originating from the ADC adds to the rest and the bandwidth is not limited. Moreover, the 1/SQRT(G) law becomes rather a 1/G law for low gain values.
ReplyDelete