VLSI Symposium Image Sensor Papers

2006 VLSI Circuits Symposium on June 15-17 presents quite a few papers on image sensors:

The most interesting paper naturally came from the market leader Micron:

A High-Performance, 5-Megapixel CMOS Image Sensor for Mobile and Digital Still Camera Applications, A. Zadeh, M. Malone, A. Bahukhandi, S. Ay, P. Amini, M. Buckley, J. Gleason, Micron Technology Inc., Pasadena, CA
This is a 5 Mega-pixel CMOS imager targeting mobile and digital still camera. The imager includes 12-bit ADC, PLL, and a serializer with 650 mega-sample-per-second throughput. The imaging cell is 2.2μm, 4-way shared architecture. The chip uses two double-date rate readout channels to perform 12 frames per second at full resolution. Its power consumption is less than 260mW and its standby current is less tha 10μA. It is fabricated in 0.18μm mixed-signal CMOS process with 8.4mm x 7.9mm chip area.

If not a typo, this is the first announced sensor having 2.2um pixel in 0.18um process - quite a significant achievement. So far, at least 0.15um process generation has been used to achieve that small pixel pitch.

Another sensor might advance the high-end DSLR capabilities to the next level in terms of low-ISO dynamic range. However, its low light properties remain to be seen. Photogate structures usualy suffer from high dark current. It's interesting to see how they control it. Also, 6-inch wafer is quite a strange choice for that large sensor.

A 76 x 77mm2, 16.85 Million Pixel CMOS APS Image Sensor, S.U. Ay, E.R. Fossum*, Micron Technology Inc., Pasadena, CA, *University of Southern California, Los Angeles, CA
A 16.85 million pixel (4,096 x 4,114), single die (76mmx77mm) CMOS active pixel sensor (APS) image sensor with 1.35Me- pixel well-depth was designed, fabricated, and tested in a 0.5μm CMOS process with a stitching option. A hybrid photodiode-photogate (HPDPG) APS pixel technology was developed. Pixel pitch was 18μm. The developed image sensor was the world’s largest single-die CMOS image sensor fabricated on a 6-inch silicon wafer.

Photron is rapidly becoming the name in very high-speed image sensors:

A 3500fps High-Speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters, M. Furuta, T. Inoue*, Y. Nishikawa, S. Kawahito, Shizuoka Univ., Hamammatsu, Japan, *Photron Ltd., Tokyo, Japan
This paper presents a high-speed CMOS image sensor with a global electronic shutter and 12bit column parallel cyclic A/D converters. The fabricated chip in 0.25um CMOS imager technology achieves the full frame rate in excess of 3500 frames per second. The in-pixel charge amplifier achieves the optical sensitivity of 19.9V/lx-s with on-chip microlens.

A controversal Rochester University sigma-delta sensor is presented too:

A 0.88nW/pixel, 99.6 dB Linear-Dynamic-Range Fully-Digital Image Sensor Employing a Pixel-Level Sigma-Delta ADC, Z. Ignjatovic, M.F. Bocko, University of Rochester, Rochester, NY
We describe a CMOS image sensor employing pixel-level sigma-delta analog to digital conversion. The design has high fill factor (31%), zero DC offset fixed pattern noise and reduced reset and transistor readout noise in comparison to other analog and digital imager readout techniques. The sigma-delta pixel design also has low power consumption: 0.88 nW/pixel at 30 fps, high dynamic range of 16 bits, intrinsic linearity, and relative insensitivity to process variations.

KAIST professor Euisic Yoon is a known generator of interesting ideas. This time it's about high DR sensor:

A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control, S.-W. Han, S.-J. Kim, J.-H. Choi*, C.-K. Kim, E. Yoon*, KAIST, Daejeon, Korea, *University of Minnesota, Minneapolis, MN
In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. There is no significant additional hardware because we use a floating-node parasitic capacitor as an analog memory. Moreover, there is no significant sacrificing of any other CIS characteristics. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB.