IEDM 2006 Surprises

IEDM gradually becomes the biggest image sensor content general IEEE conference. This year there are quite a few image sensor papers. The biggest suprise of the show is ST 3MP imager with 1.45um pixels. So ST becomes the second company after Micron, that demonstrates working 1.45um pixel . There are also Samsung and ST imagers with 1.75um pixels described in the papers.
Here is the list of all image sensor papers from the conference site:

Session 5: Displays, Sensors, and MEMS - Image Sensors

Monday, December 11, 1:30 p.m.
Continental Ballroom 4

Co-Chairs: Jan Bosiers, DALSA
Keiji Mabuchi, Sony

1:35 p.m.
5.1 Random Telegraph Signal in CMOS Image Sensor Pixels, X. Wang, P.R. Rao, A. Mierop*, A.J.P. Theuwissen, Delft University of Technology, Delft, The Netherlands, *DALSA B.V., Eindhoven, The Netherlands

RTS is observed and studied in 4T CIS pixels made in 0.18um CMOS process, the actual dominating pixel read noise is dominated by a single interface trap in the SF. The CDS influence on RTS noise is characterized and the temperature dependency measurement unveiled two mechanisms of RTS during CDS.

2:00 p.m.
5.2 Low-noise Imaging System with CMOS Sensor for High-quality Imaging (Invited), H.Sumi, Sony Corporation, Tokyo, Japan

I would like to summarize the feature of the proposed Imaging system with CMOS image sensor for high-quality imaging. Especially, I focus my discussion on the low noise technology for high quality imaging.

2:25 p.m.
5.3 H1/2.5” 8 Mega-pixel CMOS Image Sensor with Enhanced Image Quality for DSC Application, J. Kim, J. Shin, C-R. Moon, S-H. Lee, D-C. Park, H. Jeong, D. Kwon, J. Jung*, H. Noh, K. Lee, K. Koh, D. Lee and K. Kim, Samsung Electronics Co., Ltd., Gyeonggi-Do, Korea, *Sejong University, Seoul, Korea

Technology and characteristics of 8-mega density CMOS Image Sensor (CIS) with unit pixel size of 1.75x1.75um² are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera.

2:50 p.m.
5.4 Fully Optimized Cu Based Process with Dedicated Cavity Etch for 1.75um and 1.45um Pixel Pitch CMOS Image Sensors, M. Cohen, F. Roy, D. Herault, Y. Cazaux, A. Gandolfi, JP. Reynard, C. Cowache, E. Bruno, T. Girault, J. Vaillant, F. Barbier, Y. Sanchez, N. Hotellier, O.LeBorgne, C. Augier, A. Inard, T. Jagueneau, C. Zinck, J. Michailos, E. Mazaleyrat, STMicroelectronics, Crolles, France

An innovative process development for sub-2um CMOS imager sensors is described, leading to tremendous improvements on main pixel parameters like conversion gain, saturation charge, sensitivity, dark current and noise. A full 3MP demonstrator with 1.75um pixel pitch and 1.45um pixel pitch have been successfully designed, fabricated and characterized.

3:15 p.m.
5.5 CMOS Imager with Copper Wiring and Lightpipe, J. Gambino, B. Leidy, J. Adkisson, M. Jaffe, R. J. Rassel, J. Wynne, J. Ellis-Monaghan, T. Hoague, D. Meatyard, T. Kryzak, IBM Microelectronics, Essex Junction, VT

A CMOS imager technology is described using Cu wiring and a polymer lightpipe. A SiN layer on the sidewalls of the lightpipe reflects light and forms a hermetic seal, protecting the Cu wiring from ambient moisture. Using this structure, high quantum efficiency can be achieved for a 2.2 um pixel.

3:40 p.m.
5.6 A Highly Reliable Amorphous Silicon Photosensor for Above IC CMOS Image Sensor, N. Moussy*, P. Gidon*, N. Carriere*, W. Rabaud*, B. Giffard*, B. Gluck**, D. Thomas**, J. Primo**, F. Roy**, N. Casanova**, J. Regolini**, J.B. Chevrier^, F. Collet^, A.S. Ozanne-Gomila^, O. Salasca^, CEA/LETI, Grenoble Cedex, France, **STMicroelectronics, Crolles Cedex, France, ^Unaxis, Montbonnot, France

We report record performances for the reliability of amorphous silicon (a-Si:H) photosensor under high flux illumination. A fully functional VGA (3.0 um pitch) image sensor, which can withstand 90 suns (= 9 Mlux) during 26 ks, was realized by the optimization of a-Si:H parameters, the pixel structure and the reading voltage.

4:05 p.m.
5.7 High Performance Hybrid and Monolithic Backside Thinned CMOS Imagers Realized Using a New Integration Process, K.D. Munck, D.S. Tezcan, T. Borgers, W. Ruythooren, P.D. Moor, S. Sedky*, C. Toccafondi**, J. Bogaerts^ and C. Van Hoof, IMEC, Leuven, Belgium, *The American University in Cairo, Cairo, Egypt, **Galileo Avionica, Firenze, Italy, ^Cypress, Mechelen, Belgium

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages with low crosstalk were developed. The combination of a 50um EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing was performed on temporary 8 carriers.

4:30 p.m.
5.8 High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors, D. Temple, C.A. Bower, D. Malta, J.E. Robinson*, P.R. Coffman*, M.R. Skokan*, T.B. Welch*, RTI International, Research Triangle Park, NC, *DRS Infared Technologies, Dallas, TX

The paper reports on the demonstration of a 256x256 infrared focal plane array sensor integrated with readout IC using high density high aspect ratio 3-D interconnects. The 3-D integration technology is described, and results of electrical testing of the demonstration vehicle are presented.