Micron 1.75um Pixel Performance on ISSCC 2007

Fukuoka Institute of Technology put out an advance ISSCC 2007 program, even though it's password protected on the official ISSCC site.
The program containts quite a few interesting papers. First is Micron's 1.75um imager presentation:

28.5 A 1/2.5 inch 8.1Mpixel CMOS Image Sensor for Digital Cameras
K-B. Cho, M. Lee, S. Eikedal, J. Solhusvik
Micron Technology, Pasadena, CA

A 1/2.5 inch 8.1Mpixel CMOS image sensor with 1.75μm pixel pitch is designed to operate at 2.8V for digital still camera applications and down to 2.4V in mobile applications. The chip uses top and bottom multiple channels with a double-data-rate analog signal readout at a rate of 96Mpixels/s, which results in total 192Mpixels/s. With the analog gain set to 15.875 and a 12b ADC the noise floor falls as low as 3.8e-, yielding a pixel DR of 63.8dB.

It's not clear what happened with 2e- noise floor that Micron announced about 1.5 year ago. Now the performance numbers are much more modest. Also, the small DR number shows the full well capacity is quite low, about 6Ke - too low to become a viable contender for digital camera market, or even for high end camera-phone market. After a 2-year work on 1.75um pixel development it looks like Micron hits a brickwall with pixel size shrink.

Another interesting presentation comes from Canon:

28.6 A 1/2.7 inch Low-Noise CMOS Image Sensor with Double CDS Architecture for Full HD Camcorders
H. Takahashi, T. Noda, T. Matsuda, T. Watanabe, M. Shinohara, T. Endo, S. Takimoto, R. Mishima, S. Nishimura, K. Sakurai, H. Yuzurihara, S. Inoue
Canon, Ayase, Japan

A 1/2.7 inch 1944×1092pixels CMOS image sensor with multi-gain column amplifier and double noise canceller is fabricated in a 0.18μm 1P3M CMOS process. It operates at 48MHz in a progressive scanning mode at 60fps. A 2T/pixel architecture and low optical stack with micro innerlens achieve 14.8ke-/lx·s sensitivity, 14ke- saturation, 3.7erms noise and 12.2e- dark current at 60°C.

The pixel size is about 3um here, quite outdated by now. However, the noise is quite good and dark current numbers are really astounding.

Another interesting paper came form Grass Valley and Thomson Silicon:

28.7 A 2/3 inch CMOS Image Sensor for HDTV Applications with Multiple High-DR Modes and Flexible Scanning
P. Centen(1), S. Lehr(2), V. Neiss(2), S. Roth(2), J. Rotte(1), H. Schemmann(2), M. Schrieber(2), P. Vogel(2), B-K. Teng(2), K. Damstra(1)
(1) Grass Valley, Breda, The Netherlands
(2) Thomson Silicon Components, Villingen, Germany

A 3T CMOS image sensor is designed with cost-effectiveness and a high degree of flexibility in mind. It supports an optimal interaction between imager and the external processing. An overall noise level of 11.5e- (4e- for the pixel alone) is obtained along with a Qmax of more than 15ke- per pixel. The design supports 1920(H)×1080(V)p90 and 1920(H)×1080(V)i180 at a data rate of 2.7Gb/s.

It's not clear how they achieved 4e noise for 3T pixel, combined with 15K full well. Quite an achievement for 3T design.

Other notable presentations are:

28.8 A MOS Image Sensor with Microlenses Built by Sub-Wavelength Patterning
K. Toshikiyo, T. Yogo, M. Ishii, K. Yamanaka, T. Matsuno, K. Onozawa, T. Yamaguchi
Matsushita Electric Industrial, Kyoto, Japan

A MOS image sensor has digital-microlenses implemented by sub-wavelength patterning of concentric SiO2 ring walls. The sensitivity at the periphery of the imager is 3000e-/lx·s. In comparison, the sensitivity at the periphery of a conventional imager is 1300e-/lx·s. Thus, extremely uniform brightness throughout the reproduced image is demonstrated even with an angle of incidence >45°.

28.4 A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC
M. Snoeij(1), P. Donegan(2), A. Theuwissen(1,3), K. Makinwa(1), J. Huijsing(1)
(1) Delft University of Technology, Delft, The Netherlands
(2) DALSA, Waterloo, Canada
(3) DALSA Semiconductors, Eindhoven, The Netherlands

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3× shorter conversion time than a classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25μm CMOS process has a frame rate 2.8× that of a singleslope ADC while dissipating 24% more power.