Image Sensors on 2008 Symposia on VLSI Technology and Circuits

Symposia on VLSI Technology and Circuits is starting these days. The circuits part of Symposia is unusualy light on image sensor content. Only the new Aptina-NHK sensor is presented, but its performance is quite good. Only full well is a bit on the lower side, considering large pixel size of this sensor, and the dark current is not mentioned in the abstract:

A Very Low Column FPN and Row Temporal Noise 8.9M-Pixel, 60 fps CMOS Image Sensor with 14bit Column Parallel SA-ADC

S. Matsuo, T. Bales, M. Shoda, S. Osawa, B. Almond*, Y. Mo**, J. Gleason**, T. Chow**, I. Takayanagi, Micron Japan Ltd., Japan, *Micron Europe, United Kingdom, **Micron Technology, USA

A 1.25-inch optical format, 8.9M-pixel CMOS image sensor that employs a 4T pinned photodiode (P-PD) pixel and 14bit column ADCs is reported. A 14bit or 12bit digital video signal is streamed out via 16-lane low-voltage, low-power differential serial output ports in 50fps and 60fps operations, respectively. Temporal noise floor of 2.8e-rms and linear full-well of 27.8ke- were obtained at 60 fps operation. Row temporal noise and column FPN are as small as 0.31 e-rms and 0.36 e-rms, respectively.

The technology part of Symposia also has one image sensor paper by JVC describing its version of threshold voltage modulation sensor:

New Global Shutter CMOS Imager with 2 Transistors per Pixel.

M. Funaki, T. Shimizu, S. Orihara, H. Kawanaka, M. Kurihara, H. Sato, N. Katsumata, M. Oikawa, J. Higuchi, K. Oe, R. Kuga, K. Maki, T. Nishibata, Victor Company of Japan, Japan

We present a new global shutter CMOS imager with 2 transistors per pixel. The first transistor is a ring gate transistor for accumulating holes that modulate threshold voltage. The second one is a transfer gate transistor that transfers holes from a PD to the ring gate transistor at the same time in all pixels. Simple structure allows us to realize 5.4um pixel pitch, kTC noise free, and global shutter sensor using 0.35um technology.