The prior art straight transfer gate pixel has maximum potential in area A, while B potential is lower, creating a potential barrier and image lag:
Peninsula transfer gate reaches the area A, so the barrier and the lag are reduced:
One other interesting note is that the inventor is located in Hiroshima, Japan. So far, I did not know that Omnivsion has a pixel design group there.
Great idea !
ReplyDeleteIndeed, great idea. Please take a look at : "Solid-State Imaging with Charge-Coupled Devices", written by Albert Theuwissen in 1995, page 254, figure 9.4a. The CCD structure reported is exactly the same as the one in the patent of Omnivision.
ReplyDeleteThe patent says:
ReplyDelete"Before another image can be taken during a second integration period, the photodiode itself is reset. This reset occurs by applying a transfer signal to the gate of TX 120 while simultaneously applying a reset signal to the gate of RST 130. PD 110 is thus reset to approximately Vdd and the pixel cell is ready for a second integration period"
But I thought that you automatically reset the PPD to its pinning potential by the charge-transfer process (i.e., when the charges are transferred to the FD node, the PPD is reset).
Will the PPD be reset to VDD by the above method?. If it does, doesn't it introduce ktc noise (in the PPD), which is something you are trying to avoid (in combination with CDS?). Hope some of the experts can clear my doubt.
(
PPD: Pinned Photo-diode
CDS: Correlated double sampling
)
@ Please take a look at : "Solid-State Imaging with Charge-Coupled Devices", written by Albert Theuwissen in 1995, page 254, figure 9.4a.
ReplyDeleteAs far as I'm able to see in Google books, while the general idea might be close, the picture is quite different from Omnivision's. One can see it here: page 254
@ doesn't it introduce ktc noise (in the PPD), which is something you are trying to avoid (in combination with CDS?
If the PPD charge is fully transferred, there is no kTC noise in both ways to reset it. The way that Omnivision proposes is more robust, it effectively resets the photodiode even when it's charged close to the saturation.
Hiroshima, home town of sharp...
ReplyDeleteFirst of all, thanks for referencing my book.
ReplyDeleteThe CCD structure described in my book refers to a serial-parallel shift in a CCD register. Originally this sift was suffering from narrow channel effects, resulting in potential pockets and incomplete charge transfer between two CCD registers. To avoid these effects, the transfer gate got extensions that reached into the serial CCD registers.
What Omnivision is describing : the transfer from the PPD towards the FD is hampered by a narrow channel effect resulting in potential pockets in front of the transfer gate and leading to incomplete charge transfer. The solution proposed by Omnivision is creating an extension to the transfer gate that is reaching into the PPD area.
Conclusion : the same issue, the same effect and the same solution. Maybe the drawings in my book and in the patent of Omnivision do not look the same, but all the rest is identical. History is repeating itself, but this is not the first time and most probably will not be the last time either ;-)
I said that this is a GREAT idea. It may come from AT or re-invention of OV, it's not our concern. The patent office will issue the conclusion. Just remind that this is NOT a patent, but a simple application !
ReplyDeleteBet it would have high dark current though.
ReplyDeleteSo how would we clasify this? An innovation or a renovation of an old idea? Old method on a new technology or a breakthrough?
ReplyDeleteAssuming there is no other prior art, this certainly looks patentable to me in the context of a single transfer gate in a CMOS APS pixel. It doesn't mean that if you use this you don't infringe on other patents, but it means if someone else uses the same idea in a CMOS APS, then they are infringing on this patent.
ReplyDeleteIf they don't mention the prior art above in the app, then the patent will be at significant risk later.
This idea may be good for BSI application, give or take excess dark current as mentioned above, and full well reduction. The dimensions of the pennisula (or bump after fab) and left-over PPD will be pretty small. I wonder if they did a sim with real rounded corners etc.?
How does one fabricate a "transfer gate including a protrusion that extends at least partially over the photosensitive area"?
ReplyDeleteThe inventor might work for Toshiba.
ReplyDeletehttp://ci.nii.ac.jp/naid/110003671720
His name is 井原久典(Ihara; Hisanori).
All the old guys, the world is changing and innovations come everyday even there could be some appearance of similarities. If I follow your thinking, no innovation is possible !
ReplyDeleteIs it even possible to fabricate the invention claimed in this patent application?
ReplyDeleteof course you can, but the performance is another issue !
ReplyDelete"Is it even possible to fabricate the invention claimed in this patent application? "
ReplyDeleteWhy do you think its not possible? Usually the gate is a self-aligned mask for the p+, n-well Photodiode and n+ drain deposition. Extend you gate, and everything should fall in-line.
Using a simple analogy, if the PPD is a swimming pool, the protruding portion of the T-shaped gate is more like a diving board than a peninsula. It sticks out over the PPD. So the application is claiming a structure where, for example, the PPD of the bottom figure may have the same shapes as the PPD of the top figure.
ReplyDeleteI don't know how to make this, or if it's even possible at the scale of a pixel. Possibilities I came up with are non-self-aligned well formation then a T-shaped gate; a straight gate, then self-aligned well formation, and then an added gate extension; and a straight gate, then self-aligned well formation, then removal of the straight gate and replacement with a T-shaped gate.
And what about QE? Aren't the gates typically silicided, and won't that block light? And then won't QE vary with angle of incidence as the focal spot moves around on the PD?
ReplyDelete@CDM
ReplyDeleteI am not quite sure if I understand you/ your question correctly. The deep wells are indeed made before gate formation. The gate/spacers are used for p+/n+ and possibly the photodiode (with additional precautions for STI edges). Since it is BSI, probably additional wells may be required for preventing parasitic photo-generated carrier collection at circuitry.
I do hope that you realize that the pinning layer will not be present under the gate. Are you concerned about the geometry somehow?
@anonymous:
Its for BSI application; so there will not be major problems
What I'm not understanding is how you get the n-type implant for the photosensitive area to be under the "peninsula" portion of the T-shaped gate (e.g. see figure 4B and paragraphs 0035 and 0036 of the application). Aside from the lateral diffusion effects you'd have in any self-aligned transistor construction, that is.
ReplyDelete@CDM
ReplyDeleteAFAIK, one end of the "modified" photodiode (for full-depletion) n-region is aligned with the gate , the other end offset from the STI edges. So indeed, you wont have any n-type region under the gate; the gate will be on top of the substrate or special well implant. But I guess thats the whole point--> reduce the distance from any point of the collection node for easier charge-transfer. Unless I miss something!
But I think that a special Well implant at the middle of the PPD could resolve this problem. Am I wrong ?
ReplyDeleteInterestingly, over the weekend I found two separate pieces of prior art that make it easy to knock down all the claims.
ReplyDeleteI would share them, but on the off chance an employee of OmniVision or of Blakely, Sokoloff, Taylor, and Zafman reads this blog I wouldn't want to spoil the fun and profit of billable time spent looking.
:D
CDM, you wast your time :)
ReplyDelete... and mine as well ....
ReplyDeleteThanks CDM for your comments. Not a "wast" of time at all. Meanwhile, knocking down a claim is not so easy. You have to go word by word and show that word by word it all appears in some prior art claim. "Obviousness to one skilled in the art" is actually in the eyes of the examiner, and later, the jury. During the application process it is usually easy to modify the words to get a narrower patent claim allowed if the examiner has an objection to the first draft. Of course the applicability/enforceability of the patent goes down as well.
ReplyDeleteWow - 26 comments on this minor post - marketing guys need to get back from vacation so we can have some real announcements!
ReplyDelete"Not a "wast" of time at all"
ReplyDeleteMaybe he was reading too much Shakespeare
"They mock thee, Clifford; swear as thou wast wont"
or Anderson..
"Thou could'st not prize the rose and the nightingale, but thou wast ready to kiss the swineherd for the sake of a trumpery plaything"
this wast-time and shameful discussions show another face of so-called "invention" and "patent". Shame on you !
ReplyDeleteI don't know wether to laugh or cry at that. Shame is such a strong emotion often used to coerce people into actions that are for someone else’s good. If this is the grease that lubricates industry then it is indeed shameful.
ReplyDeleteHow would you implement the "special well implant"? Would that be something along the lines of a preliminary n-type implant followed by ordinary self-aligned steps to form the gate and the non-covered photodiode? This might work as a minimal one-extra-step processing, but I can foresee some challenges.
ReplyDeleteA classic research conclusion would be that more research is needed. :)
Postscript... Could the same effect that is hoped for here be implemented without extra fabrication steps by putting a notch or hole in the pinning layer mask and having a metal-1 layer in the role proposed for the gate peninsula?
This patent has been resistered in U.S.A. recently.
ReplyDelete