One challenge in building quality Ge-on-Si diodes has been the high thermal budget associated with reducing Ge dislocation densities caused by the Ge/Si lattice mismatch of 4%. Using a high aspect (AR) ratio connection between the germanium and silicon, the NoblePeak process induces in-plane tension, which extends the absorption band edge of the germanium, helping the sensor to capture night glow at peaks of 1.3μm and 1.6μm. Based on a standard 0.18μm CMOS foundry flow, process details are shown below. The team packaged the imagers with a thermoelectric cooler (-80°C) and incorporated them into a compact camera. Packaged testing of devices revealed a pixel QE of 44% at 1.3μm at full VGA resolution and 32% at half resolution.
 |
| Ge diode integration flow. a) CMOS-to-contact formation; b) deposit Ge well dielectric, pattern Ge well and high AR Si seeding stem to form dual cavity; c) grow Si epi, CMP, form n and p regions in Ge by ion implant, deposit Ge interlayer dielectric; d) form Ge contact and stacked contact to CMOS, standard BEOL, microlens formation. |
This is a great technology openning the path to many other non-silicon materials! I'm pretty sure and hope that these guys will come back.
ReplyDeleteThe advantage compared to hybridized FPA is obvious. The main question open is: what are the killer applications of such SWIR device?
killer app...interesting choice of words....
ReplyDeleteI think it was LWIR, not SWIR...?
ReplyDeleteIn IR imaging LWIR uses 8-12um atmospheric transmission window.
ReplyDeleteMWIR uses 3-5um window.
SWIR is shorter than that, relying on night glow phenomena. So it's correct, NoblePeak is SWIR.
SWIR is nominally 1000-1700 nm but gets pushed to 2300, 2400 or even 2500 nm for various reasons. It ends practically at 3000 nm where normal optical glasses become opaque. The part beyond 2500 nm is useful only in instruments not requiring atmospheric transmission.
ReplyDeleteHere is a link to the venerable SBRC chart showing the common band designations - http://www.coseti.org/atmosphe.htm
Just out of curiosity, would it be possible to substitute silicon for germanium in these processing steps? With a top-side photosensitive region FSI might continue to be competitive with BSI at smaller pixel pitch in low light. A double silicon stack on the top side might enable smaller pixel pitches in a BSI system. And, if you could do it on one side, maybe you could do it on both sides and make some tradeoffs between wire stacks and photosensing region locations (in substrate vs. on substrate, for instance).
ReplyDeleteCDM,
ReplyDeleteBSI allows complete charge transfer from the photodetection site to the charge collection site, and then from there to the FD.
This complete charge transfer is the key to low noise performance. Adding any node, metallic or n+ or p+ in between causes incomplete charge transfer, noise and usually lag. It will work fine in relatively modest lighting but in low light the shiortcomings are more apparent.
A second issue is dark current. One would have to passivate the sides of the island as well as the exposed surface in order to suppress dark current. I don't think it is likely that competitive levels would be achieved at RT.
Cool. I have another question, too...
ReplyDeleteThe fabrication seems somewhat analogous to amorphous silicon, only with germanium. My understanding is that amorphous silicon has low-light complications resulting from lattice defects between nanocrystals and from surface impurities, whereas crystalline silicon offers a lattice with fewer defects and the possibility of keeping the photosensitive region beneath the silicon surface.
Presuming similar physical effects with this "amorphous germanium", the structure shown would seem to have a relatively poor sensor (except for the IR response) on top of relatively good processing circuitry.
Would it be possible and/or useful to swap the germanium and silicon in this structure so that there's something like amorphous silicon on a crystalline germanium substrate?
Actually, silicon would not work on top, because the thermal cycle to activate the dopants in the silicon would necessarily affect the silicon transistors in the substrate. The process flow relies on the thermal sequence silicon (high) germanium (medium) metal (low).
ReplyDelete