Toward 1Gfps - Evolution of in Situ Storage Image Sensors

Open source Sensors Journal published a 19-page large review paper "Toward One Giga Frames per Second — Evolution of in Situ Storage Image Sensors" by Takeharu G. Etoh, Dao V. T. Son, Tetsuo Yamada, and Edoardo Charbon.

Abstract: The ISIS is an ultra-fast image sensor with in-pixel storage. The evolution of the ISIS in the past and in the near future is reviewed and forecasted. To cover the storage area with a light shield, the conventional frontside illuminated ISIS has a limited fill factor. To achieve higher sensitivity, a BSI ISIS was developed. To avoid direct intrusion of light and migration of signal electrons to the storage area on the frontside, a cross-sectional sensor structure with thick pnpn layers was developed, and named ―Tetratified structure‖. By folding and looping in-pixel storage CCDs, an image signal accumulation sensor, ISAS, is proposed. The ISAS has a new function, the in-pixel signal accumulation, in addition to the ultra-high-speed imaging. To achieve much higher frame rate, a multi-collection-gate (MCG) BSI image sensor architecture is proposed. The photoreceptive area forms a honeycomb-like shape. Performance of a hexagonal CCD-type MCG BSI sensor is examined by simulations. The highest frame rate is theoretically more than 1Gfps. For the near future, a stacked hybrid CCD/CMOS MCG image sensor seems most promising. The associated problems are discussed. A fine TSV process is the key technology to realize the structure.

The simulation of the electron collection shows a long path that electron travels from the backside to a collection node:

It can take quite a some time, even with -32V backside bias:

Everybody seems to talk about the potential of stacked sensors these days. Another approach that could benefit from it is compressive sensors reviewed in the other Sensors Journal paper "Compressive Sensing Image Sensors-Hardware Implementation" by Mohammadreza Dadkhah, M. Jamal Deen, and Shahram Shirani.

Abstract: The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.