EETimes: Piet De Moor, Program Manager for Specialty Imagers at Imec published a view on CMOS vs CCD for space applications: "While CMOS has become the standard in consumer electronics, the space community is still mainly relying on CCD technology. In part, that's because backside illumination processing for CMOS imagers is almost uniquely developed for 300mm wafers [probably Piet meant Imec process offerings here - ISW], whereas high-end space imagers typically use 200mm wafer technologies.
However, the space industry would well be served with a customized high-end backside illuminated CMOS imager processing platform on 200mm wafers. Given the strategic value of Earth observation, it is not surprising that governments on both sides of the Atlantic are currently supporting local initiatives in this area."
Can someone explain what the size of the wafer has to do with the application?
ReplyDeleteAlthough I am not an expert, I assume that at one point CMOS was made with smaller wafers (i.e. before they had 300mm).
I am totally missing the connection between wafer size and application.
One point coud be the substrate. To minimize dark current (i.e the signal generated by thermal mechanism and not by light) the usage of float zone silicon is very helpfull, you can gain orders of magnitude. Then FZ silicon exist (at least up to 2012) only in 200mm wafers.
DeleteHowever I think main reasons are related on economical and hystorical aspects: consumer applications require 300mm to shrink cost and most of the BSI efforts were made on consumer application at the beginning. First in doing BSI commercially available was omnivision on TSMC process. By the way, few people know that the micron site in Italy (now Lfoundry owned) was making 30% image sensors worldwide, and is a 200mm fab, BSI technology.
My thoughts: With smaller pixels (and smaller fill-factor), one has to go BSI, which is the case in the advanced 300mm process, but basically targeted towards consumer applications (mobile phones etc). So BSI technology that exists today might be tailored towards those particulars. Also backside thinning has to be developed as a process module (equipments that go with it, etc), so going to 200mm in that sense would be a reinvention in itself..
ReplyDeleteActually, Omnivision‘s BSI was first developed on 200mm wafers and was mass produced for a long time before adapting 300mm process. Also, LFoundry Italian fab has BSI capability on 200mm wafers.
DeleteWell. we can discount Omnivision as I dont think they have an eye on space applications, unless I am wrong. The other reason could be the large imager format used for space missions implying stitching capabilities, etc etc...
Deletefor space application, radiation hardness is a big concern, at this point, CMOS tech is better than CCD (thicker oxides), but what is the main reason for CCD tech dominating in space application? dark current? qe?
ReplyDeleteMaturity and hardware compatibility, plus long mission cycles that has still to catch up with CMOS.
DeleteTh modern CMOS image sensor was invented and initially developed for space applications, and technologies used in space CCDs, like BSI, were considered part of the road map from the very beginning. The subsequent lack of investment by NASA in scientific grade CMOS APS just points to the momentum of existing technologies and to some extent, the CCD guys scaring the bejesus out of science investigators. Who would want to risk their experiment and career on an "unproven" technology? It is great that ESA took the risk and has proven the space readiness of the CMOS image sensor technology, along with its manifold advantages, and that NASA is now considering it for a broader range of missions. Then again, this is almost the same length of time it took for NASA to fly CCDs on a regular basis.
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