The nub of the issue here is how to share data at high bandwidth between elements of a SW configurable chain of HW accelerators
Certainly the L1-L2 cache paradigm used in most application processors will not support this kind of processing pipeline at rates approaching 1Gpixel/sec
The nub of the issue here is how to share data at high bandwidth between elements of a SW configurable chain of HW accelerators
ReplyDeleteCertainly the L1-L2 cache paradigm used in most application processors will not support this kind of processing pipeline at rates approaching 1Gpixel/sec