Sony to Boost Image Sensor Production to 87K 12-inch Wafers per Month

Sony announces its plans to increase its production capacity for stacked CMOS image sensors in the fiscal year ending March 31, 2016 ("FY15"). This investment is intended primarily to augment production facilities used in the mastering processes and layering and futher downstream processes for stacked CMOS image sensors at Sony Semiconductor's Nagasaki Technology Center ("Nagasaki TEC") and Yamagata Technology Center ("Yamagata TEC"). The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors. The layering process refers to the layering of semiconductor chips containing back-illuminated structure pixels on top of semiconductor chips containing the circuit for signal processing.

With investments such as the one announced in February and this supplementary investment, Sony plans to increase total production capacity for image sensors from the current level of approximately 60,000 12-inch wafers per month to the level of approximately 87,000 wafers per month by the end of September 2016. The total additional investment amount is projected to be approximately 45 billion yen, comprising approximately 24 billion yen of investments in Nagasaki TEC and approximately 21 billion yen of investments in Yamagata TEC.