Insights From Leading Edge blog overviews image sensor stacking progress and recent publications. "
Given the continued, aggressive stacked CIS development underway from independent device manufacturers (IDM) and foundries it’s predictable that stacked chip adoption will occur very rapidly over the next few years."
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| Sony ISX014 Stacked dice (Chipworks) |
Just to understand the very basic principle, without being interesting in details...: how can the stacking be done? Do they bond entire wafers on top of each other? The interconnect must be something different than a soldering process. Can the contact positions be prepared in a way that adhesion force does the bond?
ReplyDelete-- Thomas
See
Deletehttp://image-sensors-world.blogspot.com/2011/09/sony-licenses-ziptronix-patents-for-bsi.html
http://www.ziptronix.com/technologies/zibond/
Sony also extended their Ziptronix licensing to DBI very recently. That gives them up to 100,000,000 electrical connections per square centimeter (1.6 micron pitch has been demonstrated -- one connect per pixel-ish).
http://image-sensors-world.blogspot.com/2015/03/marketwired-ziptronix-announces-patent.html
http://www.ziptronix.com/technologies/dbi/
Zibond is done cold (anneal to T < 250C) and covalently bonded. No adhesives or other additives.
They can either bond die to a wafer or wafer to wafer.
The vias line up and contact using the force of the bonding between two silicon wafers/dice.