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| CDS timing is given in ns |
Update: Another pixel noise reduction paper in the same Sensors journal issue is "Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors" by Assim Boukhayma, Arnaud Peizerat, and Christian Enz from EPFL and CEA-Leti. It covers mostly theoretical foundations of the pixel noise reduction.
Thanks to AT for the link!
There are about 21 or so papers in the works for this Special Issue on Photon-Counting Image Sensors previously announced. I guess a good thing about SENSORS is that they immediately publish the paper once we accepted it. I think 4 are published now. More soon.
ReplyDelete-Eric (Guest Editor-in-Chief) with Albert, Nobu, Edoardo and David
BTW, my student Jiaju Ma did a summer internship with Rambus. The work was done at Rambus, mostly unrelated to the research activity at Dartmouth (which happens to be sponsored by Rambus, thank you). Due to possible appearance of a conflict, I had Albert handle 100% of the editorial duties for this paper (thanks AT).
ReplyDeleteexcellent work! Feed_through is also used for pulling out electrons in conventional image sensor, while quantum imagers do not have this problem.
ReplyDeleteAlso I think the SAR is a must for this kind of high speed row timing.
Why SAR? It is not that fast as column ADC, you are better off with Cyclic. You confuse CDS time with row time. No need for very fast ADC to implement this CDS timing...
Delete1GHz for normal 12bit ramp is 4us. to reach 100ns you will need 40GHz(at least 20GHz is you count both rising and falling). you can see on paper, the CDS time is defined as the TF and second AD converting. And also nowadays, most of the row timing is used by TF and second AD( when I say this, means the fastest speed), so of course it is row timing.
Delete1) cyclic is not slope ADC
Delete2) good luck with column SAR clocked at 100+ MHz
3) again, why need for fast AD? Just sample reset and signal fast, one after the other, on 2 capacitors. Can then wait a few us for the conversion
Of course you can hold, but then you only do CDS for SF.
Deletetalking about the technique of SF bias current optimization to minimize 1/f, i remember there was a paper presented on IISW 2009 from prof. Kawahito's group that also mentioned a SF bias current switching technique to lower 1/f
ReplyDeleteFor the first paper, the sensitivity can not be qualified by only looking at the output noise. A signal-to-noise ratio or an input referred noise needs to be measured in order to confirm the efficiency of any noise reduction technique. This implies to determine the CG for each bias and CDS time conditions and calculate the input referred noise in each case.
ReplyDeleteThe charge transfer time seems too short. What is the measured lag? What is the row noise? What is the new conversion gain, now reduced due to the TG_null horizontal line?
ReplyDeleteFor photodiodes with typical flat pinned potential (i.e. flat spatially--no voltage pin potential positive gradient towards the tx gate) yes 100ns would seem aggressive. I believe the commonly used 500ns to 1us tx gate transfer time (to avoid lag) is only due to the lack of voltage gradient towards the tx gate (obviously if there is a true positive electric field towards the tx gate the lag-less readout can be vastly quicker then merely relying on Boltzmann thermal barrier jump that most flat pd implant profile schemes border on doing). My take on the reported results is that an unshared pixel at 130nm process node, carefully designed for lag, at say 240 to 300uV/e- conversion gain, employing this feed-through cancelling technique would seem to be able to provide reliable photon counting without RTS tail. My guess is that Rambus experiments were performed on a pd process not catered for lag at such short extreme transfer times unless data was supplied showing they were, but the source follower noise improvement does make sense and would be applicable for a pixel designed to transfer charge in 100ns. Id wager that reliable photon counting should be readily obtainable because such a voltage/timing solution is probably trivial to implement. Seems the "tg_null" line could add a minimal additional fractional fd capacitance if a correspondingly larger counter-coupling voltage was applied to make up for a low coupling ratio. No reason voltage tuning couldn't be done so that feed-through is nearly perfectly eliminated in the very low-light condition. It is a bit surprising that this hasn't been proposed earlier as feed-through in CIS without a doubt causes the source follower output lines to not only drive in wrong direction and aggravate settling, but to have mismatch in their behaviors from column-to-column due to device parameter mismatches. One can even argue that full KTC of the fd is not substracted out if the fd voltage is disturbed to a slightly different value between sample reset and sample signal (the column line aggravation can feed back to the fd causing miscorrelation in fd voltages, or dark level). CDS pulses (the vt of the source follower, for instance, will not be fully subtracted because of the slight change in source follower gain or change in Vt with body effect--this can cause fractional electron dark pixel fpn also which could limit photon counting). So in summary, I think this might seem a preferable path to pursue (in combination with sf process improvements) because it deals with both hurdles of RTS tail and mean read noise challenges.
ReplyDeleteJust noting that the impact of CG variation is dealt with in the photon counting error QIS paper mentioned by Vlad in a subsequent blog post.
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