EPFL publishes PhD Thesis "Ultra Low Noise CMOS Image Sensors" by Assim Boukhayma presenting a detailed description of the noises sources and techniques to achieve 0.4e- noise:
KTH Royal Institute of Technology, Sweden, publishes Thesis "Design considerations for a high temperature image sensor in 4H-SiC" by Marco Cristiano. The thesis discusses the approach to create a sensor for Venus Mission, capable to capture images at temperature of 460 degC at Venus surface.
Hi, I saw the PMOS SF pixel on several papers, who is the original designer please? Thanks!
ReplyDeleteGenerally PMOS, with lower hole mobility is less desireable as the SF because for the same current (speed), you need a bigger SF. Maybe with high density interconnect stacking, PMOS SF can be used more since parasitic loads can be reduced. I am not sure there is any "original" designer since use of PMOS has always been a choice. But probably Kodak and their reversed-polarity structure with lower noise and dark current was one of the first widely accepted CMOS image sensor configurations (they won the WK award). Well before that we played with PMOS at JPL but for FSI, FF considerations ruled out the larger PMOS gate.
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