MDPI
Special Issue on the 2017 International Image Sensor Workshop (IISW) gets one more TSMC paper "
A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel" by Seiji Takahashi, Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu, Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Wei-Chieh Chiang, Chun-Hao Chuang, Keng-Yu Chou, Chi-Hsien Chung, Kuo-Yu Chou, Chien-Hsien Tseng, Chuan-Joung Wang, and Dun-Nien Yaung.
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In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e− rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed."
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| A unit pixel circuit and device partition. |
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| A 45 nm stacked CIS test vehicle. |
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| TG area device optimizations |
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| (a) Regular pixel; (b) crosstalk-improved pixel. |
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