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Friday, January 26, 2018

Sony IEDM Presentation on 3-Layer Stacking Process Flow

Nikkei overviews Sony IEDM 2017 presentation on 3-layer stacked process flow for the fast image sensor presented at 2017 ISSCC:


The processing flow is:
  • The pixel, DRAM and logic wafers are manufactured using 90nm, 30nm and 40nm processes, respectively.
  • The DRAM wafer and the logic wafer are joined together, and the thickness of the DRAM wafer is reduced to 3μm
  • The DRAM and logic wafers are electrically connected with TSVs
  • The stacked wafers of the DRAM and logic are joined to the pixel wafer
  • The 3-layer wafer stack is thinned down to 130um and connected with TSVs

The numbers of TSVs connecting the pixel layer with DRAM is ~15,000 and DRAM with logic layer is ~20,000. Both of the TSVs have a diameter of 2.5μm and a pitch of 6.3μm. The 1/2.3-inch sensor has a resolution of 21.3MP and pixel size of 1.22um.
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2 comments:

  1. AnonymousJanuary 27, 2018 at 9:55 PM

    Is anyone using/incorporated these sensors with this triple stacked tech into their products?

    ReplyDelete
  2. AnonymousJanuary 28, 2018 at 8:13 AM

    it was found in a sony xperia smartphone teardown last year, it might have spread meanwhile:
    http://image-sensors-world.blogspot.co.at/2017/05/techinsights-publishes-sony-3-layer.html

    ReplyDelete

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