"We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P + /Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm 2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420-920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies."
What is the benefit of using 45nm on the top stack? For sure the bottom stack with the digital read-out would benefit, but for the SPADs (top stack), does finer pitch serve to improve performance? To guess, generating mask set on 45nm is more expensive, and a dedicated SPAD process has no reliance on any active devices (as seen on cross-section). To suggest, this would not be the cheapest option!
ReplyDeleteI 100% agree with you. It is wasting wafer cost, and no benefit of 45nm process. It is very strange design.
DeleteI am guessing it was a run offered by TSMC at the right price for this experimental work. I do find it strange that both in the IEDM paper (Dec 2017) and this follow up paper, pixel pitch is not clearly called out, and nearly obfuscated. It is only labeled in a figure as 19.8um. That strikes me as huge compared to the technology node. A similar process was used to build the Dartmouth 1Mpix QIS, also a photon counting array, with 1.1um pitch, and <0.1 e-/sec dark current (DCR). Of course the SPAD is a zillion times faster and aimed at time resolved applications.
DeleteWhy did TSMC offer them at the right price?
DeleteStealing their knowledge and know-how about SPAD?
It was a painful lesson to learn, back in the latter 90's, but free or full price, and anything in between, you really have to explain to the foundry, fully what you are doing in any new device, otherwise the foundry is unable to help and unable to optimize, especially when the foundry does not share its process in detail. This was true in early CMOS image sensors, and is true now. Only if you use the exact standard process and follow all design rules can you get away with just shipping a layout and getting a chip fabbed without sharing knowledge with the foundry. It is a cooperative ecosystem. I have found TSMC (and other foundries) to be trustworthy [with one notable exception in the late 90's with a different foundry.] In the academic environment, we faculty and students are grateful for the research support of foundries who have the vision to advance the state of the art as partners. Furthermore, our mission, in academia, is to discover and create new knowledge that helps society as a whole, and transferring that new knowledge to industry is one way that happens.
DeleteIt's not strange and not that simple. There are many reasons: (i) With an advanced bottom tier you can achieve lower power, better performance, more functionalities, etc. in very small area, and in this case you don't need such a large SPAD size on the top tier in the 3D approach. If you use a SPAD fabricated in e.g., 180/250/350nm, you will lose a lot of area in the bottom tier, i.e., it's a waste of area at the bottom side so that waste of money. Otherwise you will suffer from low fill factor (efficiency) with a smaller SPAD with an old technology. (ii) If you want to develop large SPAD arrays (e.g., Mpixel) with good fill factor, the 45nm based SPAD is much more appropriate. (iii) In addition, from the 3D integration point of view, you have to use an advance node for the top tier as well, because otherwise you have wafer mismatch (e.g., 8 inch vs 12 inch) for the wafer-to-wafer bonding. (iv) One top of the reasons, since the old technology nodes (e.g., 350, 250, and 180nm) are disappearing you need to develop a SPAD technology in an advanced process. As for the cost, it's not so expensive as you think due to the fact that there is no transistor on the top tier, i.e., SPAD device related process steps only on the top. In addition, the smaller size eventually reduces the chip cost as well. Keep in mind that it's a first result from the first run with a conservative approach. Much better results will be announced shortly.
DeletePerhaps choice of doping profiles available??
ReplyDeleteWe've optimized the technology as well as the device itself, and the doping profile optimization is one of the activities.
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