More about TSMC CIS Roadmap

Few more slides from TSMC Technology Symposium 2020 have been published at moore.live site. TSMC aims its 28nm CIS process to shrinking the pixel pitch from the current state of the art of 0.8um to 0.7um:

The next generation stacking process includes a fairly recent 12nm FinFET process for the bottom logic wafer:

Talking about the 12nm process intended use cases, TSMC mentions: "TSMC developed N12e specifically for AI-enabled IOT and other high efficiency, high performance edge devices. N12e brings TSMC’s world class FinFET transistor technology to IOT.

...Enhanced Machine Vision – insects, shadows or animals often falsely trigger connected security cameras. By moving the image classifier to the edge, the AI-enabled connected cameras can continually monitor for humans – even with facial recognition but ignore pets and insects without sending gigabytes of HD video into the cloud for inferencing."