The slides below are from the presentation of Sony full-frame sensor with sigma-delta ADC and kTC noise reduction: "7.6 - A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC" by Chihiro Okada.
And Samsungs's is here : https://underline.io/lecture/13542-7.1---a-4-tap-3.5%CE%BCm-1.2mpixel-indirect-time-of-flight-cmos-image-sensor-with-peak-current-mitigation-and-multi-user-interference-cancellation
ReplyDeleteKnowing those materials are free to get, people who spent money on registration get fooled....
ReplyDeleteExactly. The documents are starting to spread across the web:
Deletehttps://ymcinema.com/2021/03/21/presentation-of-sony-alpha-1-sensor-shows-zero-rolling-shutter-artifacts-at-250-fps/
https://ymcinema.com/wp-content/uploads/2021/03/Sony-Alpha-1-sensor-ISSCC-2021-presentation.pdf
No DRAM stacking. Using eDRAM or SRAM for buffer?
ReplyDeleteMy interpretation of the paper: the continuous output of the sensor is 30fps=1500MP/s=20ms. The readout pixel-adc is 250fps=12500MP/s=4ms (to overcome rolling shutter artifacts like 50Hz flicker of neno bulbs). They "only" need something like "large FIFOs" to buffer the different interface speeds, they dont need large ammount of "RAM" to store multiple frames. I think its not a big deal for Sony to embed large Fifos in a CIS, so they have not mentioned it in the paper?
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