Sony presents IEDM paper on pixel level stacked sensor with 2-Layer Transistor Pixel. Whereas conventional CMOS image sensors’ photodiodes and pixel transistors occupy the same substrate, Sony’s new technology separates photodiodes and pixel transistors on different substrate layers. This is said to double saturation signal level relative to conventional image sensors, widen DR and reduce noise. The new technology’s pixel structure will enable pixels to maintain or improve their existing properties at not only current but also smaller pixel sizes.
Since pixel transistors other than transfer gates (TRG), including reset transistors (RST), select transistors (SEL) and amp transistors (AMP), occupy a photodiode-free layer, the amp transistors can be increased in size. By increasing amp transistor size, Sony says it was able to substantially reduce the noise.
Nice step. Using for SPAD and dToF leads to comfortable integration of electronics like coincidence and massive improvement of PDE.
ReplyDeleteAny indicator what I am looking at in the lower picture? It looks like they transferred an ultrathin silicon wafer on top of the "photodiode layer" transistors. Or is this an aproach with laterial epitaxial regrowth? At leat it looks like both transistor layers were created before the contact layer.
ReplyDeleteVery impressive.
I ever imagined to have vertical transfer gate so that top layer only has photodiodes. We are still not there yet, but this is one step further. Nice!
ReplyDeleteHybrid bond is part of FD capacitance? Is affecting PRNU? and conversion gain? OVT did this experiment some years ago, I think also published in this blog.
ReplyDeletehybrid bonding parasitic should be very small since they are the top metal. The filling factor will be really good, and no photon-electron generated in the transistors, it is really big improvement.
DeleteWhere do you see the Cu-Cu hybrid bonding here? This is etched all the way down to the TRG. It seems a Si-Si or SiO2-SiO2 bonding and then etched. Any more information?
ReplyDeleteI think this approach was the subject of a Kodak patent quite a while ago, among several stacked CIS patents (quite early and foundational, relative to stacked sensors) and perhaps that was one of the patents acquired by OVT. Perhaps someone from Kodak knows more about this. I remember thinking at the time that the CG may be reduced but other than that it was a good idea.
ReplyDeleteSo good for large pixel size and large format. Sony always use smaller CG compare to its competitor, so it is not a problem for them.
DeleteI have a question not related to this article. If anybody knows please help me find the answer. In the active pixel array, there are active pixel areas and OB(Optical Black) pixel area, and in OB region, there are 2-4 rows of drain pixels where all nodes are connected to Vdd. I am kind of guessing that the purpose of having those pixels is for blocking electrons between the active area and OB area. I am not sure. Can anybody answer this question?
ReplyDeleteMy understanding of those dummy pixels are to provide better layout matching for pixels in the boundary in the active array (in this case that of metal interconnections). The metal pattern of OB is very different from that of active pixels because of the metal shielding; on the other hand, you can minimize the change in metal, if any, in those dummy pixels when you connect nodes to VDD.
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