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Sunday, February 06, 2022

Thesis on Current-Assisted SPAD Sensors

Vrije Universiteit Brussel publishes a PhD thesis "Current-assisted SPAD sensors fabricated in conventional CMOS process" by Gobinath Jegannathan.

"In this work, a novel SPAD sensor is presented where the novelty arises from the integration of a large absorption volume and a very small avalanche multiplication volume. Such a detector topology allows to have a thick absorption layer which leads to higher quantum efficiencies for NIR wavelengths. This integration is enabled by “current-assistance” principle where a drift field is created in the substrate by applying a potential gradient. This “current-assisted SPAD” is fabricated in a cost-effective CMOS process which is commercially available."

7 comments:

  1. Still confusing with this king of SPADs. Is that the fill-factor can be 100% (or close to) in an array?

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  2. With the FSI CA-SPAD arrays (which ultimately did not end up being functional), the fill factor was ~18 %. But with BSI sensor with 3D stacking (proposed in chapter 6), we can get towards 100%.

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    1. Would the PDP still be lower at the edge in this structure? Very novel thinking by the way with this current assist idea, great work!

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    2. With the proposed BSI pixel, there is expected to be a small loss in PDP at the edge due to crosstalk with the adjacent pixel.
      Thank you.

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  3. When can we expect such SPAD size to be 5um?
    Thank you

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    1. With the technology we have used 5 ­µm pitches are not possible. In the future, if we find a fab which can support our structures proposed in chapter 6, CA-SPADs with pitches of 5 ­µm or smaller can be possible.

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  4. This looks to be the same as McIntyre's reach-through SPAD devices, which works on the same concept as IMPATT diodes and not referenced in the thesis. It also appears similar to Sony's "charge focusing" SPADs which is also a copy of McIntyre's work.

    Same mechanism, new name. Probably IP reasons.

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