https://www.sony-semicon.com/en/technology/is/slvsec.html?cid=em_nl_20230228
Scalable Low-Voltage Signaling with Embedded Clock (SLVS-EC), is a high-speed interface standard developed by Sony Semiconductor Solutions Corporation (SSS) for fast, high-resolution image sensors. The interface's simple protocol makes it easy to build camera systems. Featuring an embedded clock signal, it is ideal for applications that require larger capacity, higher speed, or transmission over longer distances. While introducing a wide range of SLVS-EC compliant products, SSS will continue to promote SLVS-EC as a standard of interface for industrial image sensors that face increasing demands for more pixels and higher speed.
Enables implementation for high-speed, high-resolution image sensors without adding pins or enlarging the package. Supports up to 5 Gbps/lane. (As of November 2020.)
Uses the same 8b/10b encoding as in common interfaces. Can be connected to FPGAs or other common industrial camera components. With an embedded clock signal, SLVS-EC requires no skew adjustment between lanes and is a good choice for long-distance transmission. Simple protocol facilitates implementation.
SLVS-EC is standardized by the Japan Industrial Imaging Association (JIIA)
why not just jump to a PCIe?
ReplyDeleteI believe it has something to do with ECC, jitter and specific data pattern. 4.752Gbps per lane is however equivalent of PCIe 2.0, so PCIe 4.0/5.0 would make more sense IMO.
DeletePCIe will not offer the most optimal solution. This is a mipi-type protocol that is optimized for low power instead of having the highest available BW. There are other things that's not suitable such as PCIe PHY and MAC core is much more complex and higher cost than these small MIPI designs. The burst mode data transmission is also optimized in MIPI where as PCIe can only operate at its peak performance when you sustain high data transfer for extended period of time.
DeletePCIe is already on Gen6 official released spec going at 64GBuad but you never see this implemented in portable consumer electronics physical layer for things like camera links, because it uses too much power and the link bandwidth is overkill. Most of those chip to chip links still utilize PCIe Gen3 for cheaper cost and less power.
Any electronics system is designed for power/performance optimization. Sony is just making their own protocol to avoid using MIPI CDPHY, similar to what Apple did with lightening port. But look what happened, the industry moved on to USB-C and eventually they were forced to switch over.
It's been many years since Sony updated the spec to v3.0 to keep up with the industry growth.
Seemed to me, that this is a subset of MIPI CSL M-PHY with some proprietary extensions, which make it subject to licensing ...
ReplyDelete