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Thursday, May 30, 2024

Is 3D stacking for CIS unnecessary?

A recent video from GalaxyCore discusses their single wafer CIS arguing against the need for 3D stacking for higher resolution:


GalaxyCore's innovative single-wafer, high-resolution CMOS image sensor solution solves the problem of incompatibility between logic circuits and pixel technology through FPPI process and unique circuit architecture. Without the need for stacking, this advancement reduces silicon usage while maintaining performance equivalent to stacked CIS. The world's first 32-megapixel single-wafer CIS is already in mass production, and the 50-megapixel CIS has also been unveiled.

16 comments:

  1. No stacking but they still use BSI structure, right?

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  2. The need for 3D stacking depends on sensor size, functionality, performance, cost and others. It is not a black and white situation.

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    1. Correct. It's not black and white. It's also for sensors with color filter arrays. (Sorry, I'll show myself out.)

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    2. Is it true for grayscale though?

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  3. Is this will reduce half cost considering just one wafer compared to stack?And FPPI is not really related with BSI or stack process,it is just isolation right?

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  4. I think from pur image sensing point of view stacking cannot reduce total wafer consumption and you should add also stacking cost and yield loss. But stacking does offer much more room for on chip processing possibilities. Other advantage is that sensor die has smaller footprint. These may not be necessary if only basic image sensing and low production cost are required.

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    1. In an optimized stacked image sensor, the sensing part can be made in n-MOS technology, which is cheaper compared to full CMOS technology. "There is more to the picture than meets the eye" (Uncle Neil).

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    2. Albert TheuwissenMay 31, 2024 at 7:04 PM

      The previous comment was mine, Albert Theuwissen. Those familiar with Uncle Neil would have recognized it.

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  5. less sensor footprint, cheaper package. Asic die wafer often cheaper than imaging die wafer. Faster design cycle

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    1. Yes you are right ! The total process steps of pixel array wafer and logic wafer should be the same. Hybrid bonding is not that expensive when it is mastered. So stacking technology gives you a lot of degrees of freedom to optimize and enrich process quality and functions. In long turn it's the way you must go.

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  6. Could anyone explain to me what FPPI process stands for ?

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    1. Floating Poly Pixel Isolation

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    2. OK. so why is it better than stacking?

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  7. I have the same question, what is FPPI? Am we the only ignoramuses here?

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