"Embedding analog-to-digital converters (ADC) on CMOS image sensors is standard practice, but the BSI sensor’s speed required a massive increase in the amount of ADC. While modern CMOS image sensors typically have between 1,000 and 10,000 embedded ADC, the new BSI high-speed sensor has 40,000 ADC, each converting every 523 ns and generating a large amount of data to off-load from the sensor. To accomplish this task, it incorporates 160 high-speed serial outputs operating at greater than 5 Gbps. This technology is common on CPUs and FPGAs but new on a high-speed imaging sensor.
The density of ADC on the new sensor did create power management and electrical crosstalk challenges, which were solved with the help of our design and integrated production partner, Forza Silicon.
...testing of early designs revealed a higher level of ADC crosstalk in both normal imaging and binning modes than our simulation tools had predicted, causing noticeable artifacts in the images. Forza engineers discovered that the crosstalk exhibited predictable patterns and developed modeling techniques that helped us eliminate the crosstalk altogether, which in turn mitigated imaging artifacts."
I do have some questions/doubts about the QE curves. I guess that different devices (pixel sizes, different technologies besides the BSI/FSI of course) are used for the BSI and FSI, otherwise I cannot explain these curves. For instance the ratio between mono QE and colour QE is very different for the FSI and BSI at the peak QE's in B, G and R. Another remark : apparently a near-IR cut-off filter is used, most probably an interference filter ? The fall-off of the red QE is very steep between 650 nm and 700 nm. How can the QE in blue be higher for the FSI compared to the BSI, while the monochrome does the opposite at the same wavelength ? Also QE in blue around 400 nm for the BSI goes steeply down, why ?
ReplyDeleteI am afraid that here apples and oranges are compared ....
some "impressed newbie" questions ;-) How does a 12bit digitalization of pixel voltage work in 523ns? 12bit is 4096 steps, a bit of time for "preparation", i suppose "double sampling" of each pixel (or is this done in some analog way before adc)? Can someone sketch the basic principle of how the voltage after source follower that is the input of this ADC (right?) gets digitized - in a few words? There will be some counters and comparators involved, whats the clock frequency of counters in such ADCs?
ReplyDeleteIt is an easy technical solution if there is enough space on the front side. But my doubt is that infos overstate the use of BSI in the ease of implementing a high speed ADC. My guess is that ADCs are still placed outside the pixel area and in the past the usage of "inefficient" simple ramp/comparator/counter ADCs is because that they are the most area efficient. For yield reasons you want to make the additional ADC area as small as possible.
ReplyDeletePower efficiency wise the ramp/comparator/counter architecture is low because the comparator have to be active over a time which is 4096 the reaction time of the comparator. There are some tweeks to this but comparing this to a succsessive approximation conversion with take 12 steps the efficiency ratio is 4096/12~341. Otherwise the sucsessive approximation need to sample the read voltage in a capacitor and a feedback DAC which is more area but you can share an ADC among some read colums. So in practice the higher conversion speed by 341 could lead to a lower ADC area and lower power by sharing.
The ultimate in power efficiency is by operating the successive principle asynchronous. So if the comparator is finished earlier proceed to the next step. Or use different comparators for intial rough and later fine decisions with redundancy. By this you gain efficiency and speed by 10-50x too.
I would say that if you are knowing about this facts as i am working in this domain that this industry is praising some regular analog design work because the facts why some technique has reasons in the process, e.g. poly-caps, design team lacks, e.g. canon&foveon or time schedule.
This might be true, if they indeed are using an A-SAR, the sample rate of 1 ADC should be around 3.5 Msamples/s (2*number of pixels*fps/number of ADCs), which indeed seems reasonable. Probably the more challenging aspect would be to integrate 40000 ADCs on a chip (what reference buffer do you need for that), and making 40000 12-bit SARs area efficient also doesn't sounds very easy to do.
DeleteA-SAR are the perfect NO-baby (wise investement of smart people) step in architectural ADC development. It comes with lower level challenges as:
Delete1. Redundant and Variable Radix
2. Multiple or Adpative Comparator (Noise,Speed,Offset,Memory)
3. Variable Completion Time
The last one do not fit easy because different design teams often do not resolve the point what to do if clock gate is missed. I promise the solution is easy.
The detailed colum interleaving could reduce the number of ADCs. I think the BSI helps to route more row source followers outputs parallel through a single colum. So if the colum wiring RC settling is a limitation you could give a selected row more time because more of the a read in parallel. Making the colum wires themself wider do not solve the RC delay.
If you are a teacher in an Analog Design Course i think it is a good exercise to break down this hole design in 4-8 hours with calcs and sims.
@ I promise the solution is easy.
DeleteMany people promised that but no solution worked in the end. Fortunately, image sensors are somewhat less sensitive to the sparkling codes. The affected pixel data might be interpolated out similar to the pixels with large RTN.
"efficiency ratio is 4096/12~341" : You are comparing apples to oranges, as AT said above. Slope adc counts at many GHz speed. With smaller node the difference will increase. Sar Dac is analog limited to MHz speed per step. SAR is not always faster.
ReplyDeleteNo, i am comparing at the architecture level where the decision speed of the comparator only depend on how close the to be compared value is to the comparison level.
DeleteAnd please do not think in categories: "DACs are limited to MHz speed"
For most designs you can derive from the process parameters the circuit level performance values. That is a standard technique to separate process from architecture ans circuit level detail solution. It ease porting and comparison. There is no place for this kind of claims in modern design teams.
Sorry, again apples to oranges. Slope comparator can be slow, CDS will compensate delay. SAR comparator needs fast and precise. And yes, accurate DACS in small column pitch are difficult to speed up. You can share and make them bigger but then lower parallelism kills the speed advantage.
DeleteThere are some infos about fast ADCs in image sensors as well in the Sony ISSCC presentation (might be completely different from this sensor, but just a few more insights...):
ReplyDeletehttp://image-sensors-world.blogspot.com/2021/03/isscc-2021-presentations-on-line-sony.html. (I have to admit I dont really understand the topic ;-) but they say for ADC: - 14bit, 4ms readout for 50MP, Singleslope ADCs were not used in this sensor but it seems such ADCs are running at up to 2-3Ghz in image sensors, they use Deltasigma ADCs
The reason for going to Delta-Sigma is probably indeed because at 14 bit, the slope ADC will take way too long to convert, and Delta-Sigma is a better choice to reach high resolution. However, from a high-speed perspective, Delta-Sigma doesn't seem the best choice, since it is an oversampling architecture, which are always slower compared to their Nyquist rate counterparts (although "Nyquist rate" is not really applicable to image sensors).
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