Image sensor papers have a strong appearance in
IEDM 2018 Program:
1.5µm dual conversion gain, backside illuminated image sensor using stacked pixel level connections with 13ke- full-well capacitance and 0.8e- noise
V. C. Venezia, A. C-W Hsiung, K. Ai, X. Zhao, Zhiqiang Lin, Duli Mao, Armin Yazdani, Eric A. G. Webster, L. A. Grant, OmniVision Technologies
A 1.5µm pixel size, 8 mega pixel density, dual conversion gain (DCG), back side illuminated CMOS image sensor (CIS) is described having a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e- RMS at 8x gain. The sensor adopts a world smallest 1.5µm pitch, stacked pixel-level connection (SPLC) technology with greater than 8M connections, maximizing fill-factor of the photodiode and dimensions of the associated transistor dimensions to achieve a large FWC and low noise performance at the same time. In addition, by allocating transistors into two different layers, the DCG function can be realized with 1.5µm pixel size.
A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation
S. Iida, Y. Sakano, T. Asatsuma, M. Takami, I. Yoshiba, N. Ohba, H. Mizuno, T. Oka, K. Yamaguchi, A. Suzuki, K. Suzuki, M. Yamada, M. Takizawa, Y. Tateshita, and K. Ohno, Sony Semiconductor
This is a report of a CMOS image sensor with a sub-pixel architecture having a pixel pitch of 3 um. The aforementioned sensor achieves both ultra-low random noise of 0.68e-rms and high dynamic range of 121 dB in a single exposure, further realizing LED flicker mitigation.
A 24.3Me- Full Well Capacity CMOS Image Sensor with Lateral Overflow Integration Trench Capacitor for High Precision Near Infrared Absorption Imaging
M. Murata, R. Kuroda, Y. Fujihara, Y. Aoyagi, H. Shibata*, T. Shibaguchi*, Y. Kamata*, N. Miura*, N. Kuriyama*and S. Sugawa, Tohoku University, *LAPIS Semiconductor Miyagi Co., Ltd.
This paper presents a 16um pixel pitch CMOS image sensor exhibiting 24.3Me- full well capacity with a record spatial efficiency of 95ke-/um2 and high quantum efficiency in near infrared waveband by the introduction of lateral overflow integration trench capacitor on a very low dopant concentration p-type Si substrate. A diffusion of 5mg/dl concentration glucose was clearly visualized by an over 71dB SNR absorption imaging at 1050nm.
HDR 98dB 3.2µm Charge Domain Global Shutter CMOS Image Sensor (Invited)
A. Tournier, F. Roy, Y. Cazaux*, F. Lalanne, P. Malinge, M. Mcdonald, G. Monnot**, N. Roux**, STMicroelectronics, **CEA Leti, **STMicroelectronics
We developed a High Dynamic Range (HDR) Global Shutter (GS) pixel for automotive applications working in the charge domain with dual high-density storage node using Capacitive Deep Trench Isolation (CDTI). With a pixel size of 3.2µm, this is the smallest reported GS pixel achieving linear dynamic range of 98dB with a noise floor of 2.8e-. The pinned memory isolated by CDTI can store 2 x 8000e- with dark current lower than 5e-/s at 60°C. A shutter efficiency of 99.97% at 505nm and a Modulation Transfer Function (MTF) at 940nm better than 0.5 at Nyquist frequency is also reported.
High Performance 2.5um Global Shutter Pixel with New Designed Light-Pipe Structure
T. Yokoyama, M. Tsutsui,Y. Nishi, I. Mizuno, V. Dmitry, A. Lahav TowerJazz
We developed a 2.5um global shutter (GS) CMOS image sensor pixel using an advanced Light-Pipe (LP) structure designed with novel guidelines. To the best of our knowledge, it is the smallest reported GS pixel in the world. The developed pixel shows an excellent Quantum Efficiency (QE), Angular Responses (AR) and very low Parasitic Light Sensitivity (PLS). Also, even in oblique light condition of 10 degrees, the 1/PLS is maintained to about half value. These key characteristics allow development of ultra-high resolution sensors, industrial cameras with wide aperture lenses and low form factors optical modules for GS mobile applications.
Back-Illuminated 2.74 µm-Pixel-Pitch Global Shutter CMOS Image Sensor with Charge-Domain Memory Achieving 10k e- Saturation Signal
Y. Kumagai, R. Yoshita, N. Osawa, H. Ikeda, K.Yamashita, T. Abe, S. Kudo, J. Yamane, T. Idekoba, S. Noudo, Y. Ono, S.Kunitake, M. Sato, N. Sato, T. Enomoto, K. Nakazawa, H. Mori, Y. Tateshita, and K. Ohno, Sony Semiconductor
A 3208×2184 global shutter image sensor with back-illuminated architecture is implemented in a 90 nm/65 nm imaging process. The sensor, having 2.74 µm-pitch-pixels, achieves 10000 electrons full-well capacity and -80 dB parasitic light sensitivity. Furthermore, 13.8 e-/s dark current at 60°C and 1.85 erms random noise are obtained. In this paper, the structure of a pixel with memory along with saturation enhancement technology is described.
A CMOS Proximity Capacitance Image Sensor with 16µm Pixel Pitch, 0.1aF Detection Accuracy and 60 Frames Per Second
M. Yamamoto, R. Kuroda, M. Suzuki, T. Goto, H. Hamori*, S. Murakami*, T. Yasuda*, and S. Sugawa, Tohoku University, *OHT Inc.
A 16µm pixel pitch 60 frames per second CMOS proximity capacitance image sensor fabricated by a 0.18µm CMOS process technology is presented. By the introduction of noise cancelling operation, both fixed pattern noise and kTC noise are significantly reduced, resulting in the 0.1aF detection accuracy. Proximity capacitance imaging results using the developed sensor are also demonstrated.
Through-silicon-trench in back-side-illuminated CMOS image sensors for the improvement of gate oxide long term performance
A. Vici, F. Russo*, N. Lovisi*, L. Latessa*, A. Marchioni*, A. Casella*, F. Irrera, Sapienza University of Rome, *LFoundry, a SMIC Company
To improve the gate oxide long term performance of MOSFETs in back side illuminated CMOS image sensors the wafer back is patterned with suitable through-silicon-trenches. We demonstrate that the reliability improvement is due to the annealing of the gate oxide border traps thanks to passivating chemical species carried by trenches.
High-Performance Germanium-on-Silicon Lock-in Pixels for Indirect Time-of-Flight Applications
N. Na, S.-L. Cheng, H.-D. Liu, M.-J. Yang, C.-Y. Chen, H.-W. Chen, Y.-T. Chou, C.-T. Lin, W.-H. Liu, C.-F. Liang, C.-L. Chen, S.-W. Chu, B.-J. Chen, Y.-F. Lyu, and S.-L. Chen, Artilux Inc.
We investigate and demonstrate the first Ge-on-Si lock-in pixels for indirect time-of-flight measurements. Compared to conventional Si lock-in pixels, such novel Ge-on-Si lock-in pixels simultaneously maintain a high quantum efficiency and a high demodulation contrast at a higher operation frequency, which enable consistently superior depth accuracies for both indoor and outdoor scenarios. System performances are evaluated, and pixel quantum efficiencies are measured to be more than 85% and more than 46% at 940nm and 1550nm wavelengths, respectively, along with demodulation contrasts measured to be higher than 0.81 at 300MHz. Our work may open up new routes to high-performance indirect time-of-flight sensors and imagers, as well as potential adoptions of eye-safe lasers (e.g. wavelengths longer than 1.4µm) for consumer electronics and photonics.
CMOS-Integrated Single-Photon-Counting X-Ray Detector using an Amorphous-Selenium Photoconductor with 11×11-µm2 Pixels
A. Camlica, A. El-Falou, R. Mohammadi, P. M. Levine, and K. S. Karim, University of Waterloo
We report, for the first time, results from a single-photon-counting X-ray detector monolithically integrated with an amorphous semiconductor. Our prototype detector combines amorphous selenium (a-Se), a well known X-ray photoconductive material suitable for large-area applications, with a 0.18-µm-CMOS readout integrated circuit containing two 26×196 photon counting pixel arrays. The detector features 11×11-um2 pixels to overcome a-Se count-rate limitations by unipolar charge sensing of the faster charge carriers (holes) via a unique pixel geometry that leverages the small pixel effect for the first time in an amorphous semiconductor. Measured results from a mono-energetic radioactive source are presented and demonstrate the untapped potential of using amorphous semiconductors for high-spatial-resolution photon-counting Xray imaging applications.
High Performance 2D Perovskite/Graphene Optical Synapses as Artificial Eyes
H. Tian, X. Wang, F. Wu, Y. Yang, T.-L. Ren, Tsinghua University
Conventional von Neumann architectures feature large power consumptions due to memory wall. Partial distributed architecture using synapses and neurons can reduce the power. However, there is still data bus between image sensor and synapses/neurons, which indicates plenty room to further lower the power consumptions. Here, a novel concept of all distributed architecture using optical synapse has been proposed. An ultrasensitive artificial optical synapse based on a graphene/2D perovskite heterostructure shows very high photo-responsivity up to 730 A/W and high stability up to 74 days. Moreover, our optical synapses has unique reconfigurable light-evoked excitatory/inhibitory functions, which is the key to enable image recognition. The demonstration of an optical synapse array for direct pattern recognition shows an accuracy as high as 80%. Our results shed light on new types of neuromorphic vision applications, such as artificial eyes.
Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness
J. Jourdon,, S. Lhostis, S. Moreau**, J. Chossat, M. Arnoux***, C. Sart, Y. Henrion, P. Lamontagne, L. Arnaud**, N. Bresson**, V. Balan**, C. Euvrard**, Y. Exbrayat**, D. Scevola, E. Deloffre, S. Mermoz, A. Martin***, H. Bilgen, F. Andre, C. Charles, D. Bouchu**, A. Farcy, S. Guillaumet, A. Jouve**, H. Fremont*, and S. Cheramy**, STMicroelectronics, *University of Bordeaux, **CEA-LETI, ***STMicroelectronics
We present the first 3D-stacked CMOS Image Sensor with a bonding pitch of 1.44 µm. The influence of the hybrid bonding pitch shrinkage (8.8 to 1.44 µm) from the process point of view to a functional device via the robustness aspect is studied. Smaller bonding pads do not lead to any specific failure.
Few other papers that are not directly related to imaging, but might become more relevant some day:
100-340GHz Systems: Transistors and Applications (Invited),
M.J.W. Rodwell, Y. Fang, J. Rode, J. Wu, B. Markman, S. T. Suran Brunelli, J. Klamkin, M Urteaga*, University of California, Santa Barbara, *Teledyne Scientific Company
We examine potential 100-340 GHz wireless applications in communications and imaging, and examine the prospects of developing the mm-wave transistors needed to support these applications.
High Voltage Generation Using Deep Trench Isolated Photodiodes in a Back Side Illuminated Process
F. Kaklin, J. M. Raynor*, R. K. Henderson, The University of Edinburgh, *STMicroelectronics Imaging Division
We demonstrate passive high voltage generation using photodiodes biased in the photovoltaic region of operation. The photodiodes are integrated in a 90nm back side illuminated (BSI) deep trench isolation (DTI) capable imaging process technology. Four equal area, DTI separated arrays of photodiodes are implemented on a single die and connected using on-chip transmission gates (TG). The TGs control interconnects between the four arrays, connecting them in series or in parallel. A series configuration successfully generates an open-circuit voltage of 1.98V at 1klux. The full array generates 423nW/mm2 at 1klux of white LED illumination in series mode and 425nW/mm2 in parallel mode. Peak conversion efficiency is estimated at 16.1%, at 5.7klux white LED illumination.
Error-Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approach
X. Zheng, R. Zarcone*, D. Paiton*, J. Sohn, W. Wan, B. Olshausen* and H. -S. Philip Wong, Stanford University, *University of California, Berkeley
We demonstrate by experiment an image storage and compression task by directly storing analog image data onto an analog-valued RRAM array. A joint source-channel coding algorithm is developed with a neural network to encode and retrieve natural images. The encoder and decoder adapt jointly to the statistics of the images and the statistics of the RRAM array in order to minimize distortion. This adaptive joint source-channel coding method is resilient to RRAM array non-idealities such as cycle-to-cycle and device-to-device variations, time-dependent variability, and non-functional storage cells, while achieving a reasonable reconstruction performance of ~ 20 dB using only 0.1 devices/pixel for the analog image.
