Thursday, July 28, 2011

Omnivision Proposes PR Thinning to Improve Pinned PD Alignment in Small Pixels

Omnivision's US20110177650 patent application proposes photoresist thinning to improve alignment between the edge of the photodiode and the pinning layer. The prior art uses photoresist masks 140 and 142 for photodiode 130 and p+ pinning layer 165 implants respectively:


"The alignment of dopant region 165 to dopant region 135 is not only important at the transfer gate edge. In fact, at all other locations around the periphery of the photodiode it is preferable that pinning photodiode dopant region 165 fully enclose photodiode dopant region 135, i.e., that dopant region 165 preferably extends beyond the borders of dopant region 135. Ion implant shadowing on the sides of the pixel opposite to the transfer gate produces offsets opposite to those provided at the transfer gate edge. The layout design and alignment of photoresist masks 140 and 142 preferably anticipate this in order to meet the above stated preference for placement of dopant region 135.

As CIS pixel design and fabrication technologies advance, pixel sizes decrease in order to provide more pixels per unit area. Alignment tolerances often cannot be decreased in proportion to decreases in pixel element dimensions and, in particular for the pinned photodiode pixel elements, the cathode element is made to shrink more than the anode element in order to compensate for retained alignment tolerances. This may result in an accelerated decline of the full well capacity and therefore a decline in performance of the pinned photodiode pixel
."

Omnivision proposes that "an isotropic resist etching (resist trim) process is applied to photoresist mask 140 to reduce the thickness and other dimensions of photoresist mask 140 by a designed amount. Thus, trimmed photoresist mask 145 is self aligned to original photoresist mask 140":


"The alignment of dopant regions 535 to 565 is determined by the transfer gate edge in the region adjacent to the transfer gate as in the conventional process. The alignment of dopant regions 535 and 565 in locations other than adjacent to the transfer gate is determined by the self aligned masks as described herein. This results in reduced manufacturing cost due to fewer photoresist masks and in larger full well capacity due to a larger pinned photodiode cathode area compared to the conventionally fabricated CIS pixel."

Another version of Omnivision's application talks about transfer gate formation after all photodiode and pinning layers implants are complete. In that case the gate is not self-aligned with the photodiode.

1 comment:

  1. Can believe they are trying to patent this. Well known and obvious for general application to CMOS.

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