Wednesday, October 12, 2011

More about Caeleste 4T Pixel with 0.5e Noise

Caeleste monthly newsletter that I was kindly offered to subscribe to has a more detailed description of its 4T pixel with 0.5e- noise:

"After reduction of kTC, EMI and thermal noise, the fundamental limit in noise in CMOS 4T pixel is the 1/f noise contribution of the source follower. It is generally accepted that the 1/f noise and RTS noise in MOSFETs is adequately explained and modeled by the McWorther theory. Charge carriers in the MOSFET’s inversion layer are captured and released, by interface states or oxide traps, acting as spurious energy levels inside the band gap. Traps that have energies close to the Fermi level of the MOSFET channel have an equilibrium occupancy probability that obeys the Fermi-Dirac statistics. For a given trap energy level, one may have a huge spread of emission and capture time constants.

In literature it is observed that this time correlation between samples can be broken by periodically pulsing the MOSFET to accumulation between samples. When returning to inversion, the long term “memory” of the trap has disappeared. The MOSFET’s noise spectrum becomes white, the signature of “uncorrelation”. Caeleste patented pixel includes a simple, compact charge trans-impedance amplifier (CTIA). The feedback capacitance is the gate-drain overlap of the driver MOSFET, and in the order of 0.1fF, resulting in an effective CVF between 1000 and 1100 μV/electron. The uncorrelation between samples allows the column electronics to reduce the (1/f) noise by Oversampling.
"

11 comments:

  1. Has anyone been able to locate the referenced patent? I tried and failed at the USPTO website.

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  2. maybe this one: US2010/0252717 , figure 4?

    (link: http://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20101007&DB=EPODOC&locale=nl_be&CC=US&NR=2010252717A1&KC=A1)

    Benoit or Bart, can you comment?

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  3. All the major CMOS Fabs are working on the 1/f reduction by their process. This kind of "invention" on the paper has no big practical value. The side effect in their complexe electronics will rais more problems than it can resolve.

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  4. One thing that I'm unable to understand is how the source follower MOSFET can be put in accumulation. It would require either a negative voltage on the floating diffusion or a very high Vth of the source follower so that zero voltage on FD can produce accumulation.

    Negative voltage on FD would result in a huge dark current, while high Vth would kill pixel output swing. So, how do they put it in accumulation?

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  5. This is a bit of a digression, but does anyone know who provides the CMOS image sensors used in the cameras for the SAMSUN GALAXY S2 phone?

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  6. Chipworks knows:

    http://www.chipworks.com/en/technical-competitive-analysis/resources/recent-teardowns/2011/07/silicon-summary-in-the-samsung-galaxy-s-ii/

    Both primary 8MP and secondary 1.9MP sensors are made by Samsung. The 8MP one is 1.4um-pixel BSI part. The 1.9MP one is S5K5BAFX.

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  7. Hi Guy,

    No it is not that one. The patent is not out yet.

    As usual, Anonymous user can write my direction if he really wants information instead.

    We will show more stuff at the CNES workshop in december in Toulouse. I think some of you will be there anyway and I'll be happy to talk to you guys there.

    Cheers.

    Benoit Dupont

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  8. From a characterization standpoint, does this mean that a pixel operating with this pulsed accumulation method will no longer reveal the tri-modal noise distribution commonly observed on a conventional RTS pixel?

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  9. >> One thing that I'm unable to understand is how the source follower MOSFET can be put in accumulation.
    I suppose the SF is forced into accumulation when the pixel is not selected. An NMOS device will go into accumulation if you raise the source terminal above the gate terminal (FD). When the SF is not selected the source terminal is normally floating and sits <Vt below the gate. They may use one more switch to pull the source terminal to vdd (or sufficiently high) when the SF is not selected.

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  10. Sorry, I disagree. The accumulation mode depends on gate to bulk potential. Source or drain can not do it. Forcing SF source high leaves SF in depletion, rather than in accumulation region.

    I recall a paper in Electron Device Letters few months ago also calling the pulling the SF source up to be the accumulation mode. It's not. It's just a depletion. The measurements in this paper have shown some noise reduction, even though SF lacks accumulation.

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