A-SSCC Circuit Insights CMOS Image Sensor

 

A-SSCC 2025 - Circuit Insights #4: Introduction to CMOS Image Sensors - Prof. Chih-Cheng Hsieh

About Circuit Insights: Circuit Insights features internationally renowned researchers in circuit design, who will deliver engaging and accessible lectures on fundamental circuit concepts and diverse application areas, tailored to a level suitable for senior undergraduate students and early graduate students. The event will provide a valuable and inspiring opportunity for those who are considering or pursuing a career in circuit design.

About the Presenter: Chih-Cheng Hsieh received the B.S., M.S., and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 1990, 1991, and 1997, respectively.,From 1999 to 2007, he was with an IC Design House, Pixart Imaging Inc., Hsinchu. He led the Mixed-Mode IC Department, as a Senior Manager and was involved in the development of CMOS image sensor ICs for PC, consumer, and mobile phone applications. In 2007, he joined the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, where he is currently a Full Professor. His current research interests include low-voltage low-power smart CMOS image sensor IC, ADC, and mixed-mode IC development for artificial intelligence (AI), internet of things (IoT), biomedical, space, robot, and customized applications.,Dr. Hsieh serves as a TPC member of ISSCC and A-SSCC, and an Associate Editor of IEEE Solid–State Circuit Letters (SSC-L) and IEEE Circuits and Systems Magazine (CASM). He was the SSCS Taipei Chapter Chair and the Student Branch Counselor of NTHU, Taiwan.

Time-mode CIS paper

In a recent paper titled "An Extended Time-Mode Digital Pixel CMOS Image Sensor for IoT Applications" Kim et al from Yonsei University write:

Time-mode digital pixel sensors have several advantages in Internet-of-Things applications, which require a compact circuit and low-power operation under poorly illuminated environments. Although the time-mode digitization technique can theoretically achieve a wide dynamic range by overcoming the supply voltage limitation, its practical dynamic range is limited by the maximum clock frequency and device leakage. This study proposes an extended time-mode digitization technique and a low-leakage pixel circuit to accommodate a wide range of light intensities with a small number of digital bits. The prototype sensor was fabricated in a 0.18 μm standard CMOS process, and the measurement results demonstrate its capability to accommodate a 0.03 lx minimum light intensity, providing a dynamic range figure-of-merit of 1.6 and a power figure-of-merit of 37 pJ/frame·pixel. 

 

Figure 1. Operation principle of conventional CISs: (a) voltage mode; (b) fixed reference; and (c) ramp-down TMD.

Figure 2. Theoretical photo-transfer curve of conventional 6-bit TMDs.

Figure 3. The operation principle of the proposed E-TMD technique.

Figure 4. Theoretical photo-transfer curve of the proposed E-TMD: (a) TS = TU = TD = 2000tCK, Δ = 0; (b) TS = TU = TD = 100tCK, Δ = 0; (c) TS = TU = 0, TD = 45tCK, Δ = 0; and (d) TS = 0, TU = 25tCK, TD = 45tCK, Δ = 0.7.

Figure 5. The conventional time-mode digital pixel CIS adapted from [11]: (a) architecture; (b) pixel schematic diagram.

Figure 6. Architecture and schematic diagram of the proposed time-mode digital pixel CIS.

Figure 7. Operation of the proposed time-mode digital pixel CIS with α representing VDD-vREF-VT: (a) six operation phases and (b) timing diagram.

Figure 8. Transistor-level simulated photo-transfer curve comparison.

Figure 9. Chip micrograph.

 

Figure 10. Captured sample images: (a) 190 lx, TS = 17 ms, tCK = 50 µs; (b) 1.9 lx, TS = 400 ms, tCK = 2 µs.

Figure 11. Captured sample images and their histograms: (a) 20.5 lx, TS = 32.6 ms; (b) 200.6 lux, TS = 4.6 ms; (c) 2106 lux, TS = 0.64 ms; (d) 2106 lux, TS = 0.64 ms, TU = 0.74 ms, TD = 1.84 ms, Δ = 0.5.