Saturday, January 29, 2011
News from EI 2011 - Part 3
Albert Theuwissen continues to share his impressions from Electronic Imaging 2011 conference. The concluding part talks mainly about Toshiba paper “Dark noise in a CMOS imager pixel with negative bias on transfer gate”, by Hirofumi Yamashita et al. The negative bias is said to greatly reduce hot pixels, but increase number of warm pixels. The solution is not too surprising - reduce electric field between Tx gate and floating diffusion.
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The Semiconductor Interface Specialists Conference (SISC) has been operating for about 42 years. I used to attend this meeting regularly coming out of Yale where I was about the only student not working directly on semiconductor interface problems. It was the initial model for the IISW. I have not been there for a while but I highly recommend it for anyone who is interested in MOS interfaces. It usually meets just prior to the IEDM.
ReplyDeleteThe moral of this post is that the physics of the MOS interface is complex and there has been an annual conference for 42 years and still much to learn, as Albert points out.
To Vladimir : everything becomes not too surprising if the answer is known ... ;-)
ReplyDeleteThis topic has been addressed several times now.
ReplyDeletethe most important and also the most difficult thing is to link a certain phenomenum to a certain physical origin.
ReplyDeleteYou can see such arrangement in the CMOS Pixel DR of several major CMOS foundries.... by using LDD.
ReplyDeleteThere is a big difference between doing a semi-random walk thru process and design splits (which is a time-efficient method of optimization), and finding a root cause thru the scientific method. Of course everyone knows that LDD is important for reducing e-field and its positive effect on dark current.
ReplyDeleteIt is also true that almost all bad things with MOS device performance since the 1960's have been blamed on interface traps. It is usually correct, but scientifically proven and understood only with great effort.
I do think that the process guys in such CMOS foundries do "fundamental" research. But they will never publish such kind of stuffs considered as commercial secrets, I think that it is always "random" and "drunk man" optimization.
ReplyDeleteSo there should be the same problem in a 3T pixel design too in this case. When the RESET NMOS is turned off, there is a strong negative voltage between the gate and the source (PD).
ReplyDelete