Thursday, January 24, 2013

Samsung Proposes High Voltage Bias on Sensor's Backside

Samsung patent application US20130015325 "Backside illuminated image sensor" by Jung-Chak Ahn proposes to use relatively thick BSI substrate (10um in an example embodiment) and apply high voltage on the backside to reduce crosstalk. The backside voltage is provided by a charge pump. Unfortunately, the application does not tell what to do with current flow from the backside voltage source (-10V in the example below) through the p-type inter-PD isolation to the front side p+ pinning layer at 0V.

21 comments:

  1. A large backside bias for a thick BSI substrate is well known. What's the invention here?

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    1. Known? Do you mean somebody already applied 0V on the frontside pinning layer, large negative voltage on the backside, got few ampers of DC current through the substrate, and published this somewhere?

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  2. There are a class of patent applications you have to file because if your competitor files it and the claims are allowed, you will feel kind of dumb.

    Also, I did not read the app but I can imagine many variations on the basic old CCD ideas that could result in some claims being allowed.

    Lastly, Vlad, if there is isolation by depletion and n+ implant on the backside, then the imaging area may not be shorted from back to front as you suggest.

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    1. Eric, you meant p+ backside implant, right? The depletion isolation between PDs was the first thing I looked in the application. Unless I overlooked, it says nothing about that. It's not easy to build, assuming one needs to get a good isolation between the PD sides and in corners, also when PD is fully discharged or even forward biased by a strong light. Or something should prevent it from the full discharge. The application does not talk about it either.

      So far I have not seen anybody achieving this in CMOS. Am I missing something?

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  3. Vladimir, people have achieved this but not everybody publishes all they are doing. People like to keep trade secrets, some of those are actually well known by the experienced players in the market, but they form a kind of entry barrier for newbies. If you publish the, often simple, tricks, it could get crowded. The many tricks required in pixel timing to avoid ugly artefacts are a good example. Everybody knows them, but it's hard to find publications on the same.

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    1. Finally back home from a day of meetings... What can I say on this... it's quite mystifying answer. Well, assuming people have done this, I can think of many possible applications that would show up on the market:

      1. Backside bias can be used as a sensitivity modulator for a ToF imager. Such ToF sensor can be nicely combined with RGB one, in the same array. It's quite easy, why don't we see it in the products yet?

      2. One can use backside bias as a nice global shutter, no need in 5T, 7T and other ugly pixels. We could easily make 2.2um or, may be, even 1.75um pixels as a regular 4T and with global shutter. So far, I have not seen them on the market though.

      So, my question to the people who makes these wonderful pixels, why don't you use your killer advantage? You don't want to capture the whole image sensor market?

      To be serious, the closest pixel I can think of is described here, but it's not quite the same:

      http://www.imagesensors.org/Past%20Workshops/2011%20Workshop/2011%20Papers/P32_Lauxtermann_ThickBSI.pdf

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    2. If I remember well, there was a back-side illuminated CCD (thick substrate) by Lincoln Lab MIT that used a backside-contact to operate the device with a kind of shutter.
      After searching I found it back : presented at IEDM 1991 by R.K. Reich.

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    3. Thanks. But this was done in CCDs, in a whole different world. I wonder if somebody managed to isolate the frontside p+ pinning layer from the backside p+ layer, in CMOS sensor. So, when there is a 10V potential difference between them, no significant DC current flows. Preferably, the PD should be fully pinnable, so that 4T pixel with CDS can be implemented.

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    4. Manage. I know someone who uses n-- bulk for that.

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    5. n-- bulk... This can work. But it's quite a departure from what Samsung is describing.

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    6. You can also have a look here: http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1340970

      I personally do not get this patent system. I could patent things like that every week.

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    7. Thanks. Just like in the patent application in the comment below, they use 10,000 Ohm-cm epi, very far from the CMOS process mainstream.

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    8. Albert/Vladimir,
      Can you share that BSI presentation with me at pchavva@cmocast.net
      Regards,
      Venkat

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    9. Venkat, I do not have this one as a soft copy, you can find it on IEEExplore.

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  4. When I first read this I could have sworn that the headline said "Senator's Backside". Now I see that the subject is not nearly as satisfying.

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  5. US 2010/0116971 seems sort of similar. US 2011/0024808 might be relevant also.

    US 8339494 isn't related but it is interesting nonetheless. It dumps charge across the substrate from backside photodiodes to frontside photodiodes in order to read it out.

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    1. Thanks for the references! Let's see:

      US2010/0116971 has front pinning layer shorted with the backside by design. So, when backbiasing, front and back have the same potential. This is different from the Samsung application in the post.

      US2011/0024808 is similar to the Samsung application, and shows a simulation result with the substrate current blocked on Fig 4B. However, the substrate in the simulation has 10,000 Ohm-cm resistivity, far away from the CMOS process mainstream.

      The US8339494 is a very nice idea, went from filing to granting at a rocket speed. I wonder whether it works well in silicon, and what is the image lag of the 2 PD system.

      If these or similar ideas perform well in silicon, we all will wake up in a different world:

      - all sensors will have GS
      - all sensors will support ToF mode
      - end of QE tyranny - QE is always 100%, unless somebody saved on AR layers (well, the blue one might be a bit lower, also CFA adds some losses)
      - no diffusion crosstalk, from that time on electrons only drift, do not diffuse anymore

      If this happens, I would be very surprised.

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  6. Hello Vladimir,
    Could you please explain to me why these sensors will have GS? Where would be the storage node? You mean that by applying certain backside biasing this would block the photon integration acting as a mechanical shutter? Sorry, I'm not a physicist..

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    1. There is no need to have storage node. When the backside bias is applied the pixels are sensitive to light. If we do not apply the negative bias, the depletion does not extend much, so there is a thick layer of neutral silicon on the backside. If the layer is thick enough, the light does not reach the PDs. Photoelectron diffusion can be blocked by a potential barrier of some sort, so that they do not reach PDs.

      Making the GS fast for ToF takes a little more effort, but it's possible too.

      Actually, such a sensor opens o lot of other possibilities. For example, if the backside bias voltage has a gradient, i.e. from left to right or from top to down, the drifting photoelectrons can be deflected to the neighboring pixels. That way a solid state image stabilization can be implemented, given a gyro signal to control image shift is available.

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  7. Thanks for the answer! Very clear. Indeed great advantage. Only drawback is that during readout operation, the sensor cannot gather light. It is a kind of discontinuous sensing. Peanuts compared to the advantages..

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  8. Not necessarily discontinuous. Out of the patents mentioned in comments, at least one, the US8339494 allows pipelining. Still, I'm quite skeptical that this and other ideas above would be successfully implemented in the consumer grade sensors.

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