This graph perfectly captures the race to increase the pixel conversion gain while the rest of the readout channel suffers from bad noise optimization. Thanks for a fresh perspective.
No, the curve captures the problem of shrinking the SF contribution to capacitance while unfortunately increasing its 1/f noise. Your ill-informed comment ignores the fact that the read noise in input-referred electrons is being reduced.
Actually, more likely a combination of both. <100uV read noise is also challenging, especially with ever decreasing column pitch. The right question may also be: how accurate is that 30uV reported number... (?)
Eric, Can you compare "120uV - 0.3e- (inp referred) - Very high CG" Vs "30uV - 0.7e- (inp referred) - Low CG" cases and try to say again what you said? Why do you think it is only the optimization of SFD capacitance which results in higher 1/f? Why cannot it be a bad job in the rest of the readout channel, since one is only interested in the pumping up the pixel CG?
Its like - I don't care if my CDS operation in Column is noisy, since I am pumping up my signal by increasing e- to V ratio.
I think the 120uV rms noise is probably coming from the first in-pixel SF. If it is coming from elsewhere in the readout signal chain then yes, it could be non-optimal signal chain design.
Actually, I wouldn't call it 'non-optimal design' or 'bad noise optimization' ... at low enough speed and with infinite power budget, until something fundamental like SF RTS noise is limiting (*), then the noise in the signal chain can be made arbitrarily low. The 'optimization', however needs to take speed and power budget into account and if they met the lowest ever noise in e- within their speed and power budget, it would not be fair to state they did a bad job.
So it's more like: "my CDS operation is low-noise enough, and I am meeting my power budget thanks to a high conversion gain"
-wismerhill
(*) and even that can be overcome
B. Dierickx and E. Simoen, “The decrease of ‘random telegraph signal’ noise in metal-oxide-semiconductor field-effect transistors when cycled from inversion to accumulation,” J. Appl. Phys., vol. 71, no. 4, pp. 2028 –2029, Feb. 15, 1992
"lowest ever noise in e- within their speed and power budget" - how sure are you that they will be able to squeeze to the lowest possible noise in e-/given speed and power? If I tell 10 designers to design a readout channel, I am sure they all will come back different noise numbers/given speed and power. And the designers who do not know that I have set extremely high e-to-v CG in my pixel do the best job in designing that readout channel. You are assuming an ideal case, while we are talking about real people publishing real work.
That is why - bumping up the pixel CG gain gives you a leeway and relaxes the constraints in such a way that people start to forget about the optimization needed in the analog channel.
"how sure are you that they will be able to squeeze to the lowest possible noise in e-/given speed and power"
Did I say they got the lowest possible noise? Please read again please.
They did, as per the graph in Alberts' report, reach the lowest noise in e- ever.
"in such a way that people start to forget about the optimization needed "
You are making assumptions here. Perhaps there is more room for improvement, maybe there is not. As I said, it is possible they called it a day when they got the lowest noise in e- ever reported within their speed and power budget. That doesn't mean that they "forgot" about anything.
Bumping up the CG gives you leeway to achieve the same e- noise with lower power, but because you (and your competitors) have access to technology with higher CG, the market will expect you to lower power at the same noise, or keep power at lower noise.
Of course different designers will do better at optimizing the trade-off, but any good analog designer does not "forget" about such obviously needed optimizations.
If you go for the lowest noise possible, independent of any other parameter, then every single micro-volt of noise counts, the one in the readout channel maybe less that the others, but you should "fight" for every single micro-volt. And that makes the work of those who go for the electrons as challenging as the work of those who go for the micro-volts.
Albert, your achievement of 30uV noise from SF is great and it's far better than any actual design. Could you please give some hints on this performance please? Thanks!!!
See my literature list on www.harvestimaging.com/publications.php and check for the work of Yue Chen, especially nr. 178. There are two main technologies applied : buried channel SF to lower noise in general and 1/f in particilar, and correlated multiple sampling with column-level ADC based on digital counters with BWI.
-slow amplifier with high capacitive load=high area -fast amplifier with multiple sampling ADC=much higher power consumption. You are better off using multiple sampling through analog integrators or by using sigma delta ADC
Could someone point to this ISSCC 2012 paper which shows 30uV read noise?
ReplyDeleteSee Chen's paper on my publication list no. 178.
ReplyDeleteThis graph perfectly captures the race to increase the pixel conversion gain while the rest of the readout channel suffers from bad noise optimization. Thanks for a fresh perspective.
ReplyDeleteNo, the curve captures the problem of shrinking the SF contribution to capacitance while unfortunately increasing its 1/f noise. Your ill-informed comment ignores the fact that the read noise in input-referred electrons is being reduced.
DeleteActually, more likely a combination of both. <100uV read noise is also challenging, especially with ever decreasing column pitch. The right question may also be: how accurate is that 30uV reported number... (?)
DeleteEric, Can you compare "120uV - 0.3e- (inp referred) - Very high CG" Vs "30uV - 0.7e- (inp referred) - Low CG" cases and try to say again what you said? Why do you think it is only the optimization of SFD capacitance which results in higher 1/f? Why cannot it be a bad job in the rest of the readout channel, since one is only interested in the pumping up the pixel CG?
DeleteIts like - I don't care if my CDS operation in Column is noisy, since I am pumping up my signal by increasing e- to V ratio.
I think the 120uV rms noise is probably coming from the first in-pixel SF. If it is coming from elsewhere in the readout signal chain then yes, it could be non-optimal signal chain design.
DeleteActually, I wouldn't call it 'non-optimal design' or 'bad noise optimization' ... at low enough speed and with infinite power budget, until something fundamental like SF RTS noise is limiting (*), then the noise in the signal chain can be made arbitrarily low. The 'optimization', however needs to take speed and power budget into account and if they met the lowest ever noise in e- within their speed and power budget, it would not be fair to state they did a bad job.
DeleteSo it's more like: "my CDS operation is low-noise enough, and I am meeting my power budget thanks to a high conversion gain"
-wismerhill
(*) and even that can be overcome
B. Dierickx and E. Simoen, “The decrease of ‘random telegraph signal’ noise in metal-oxide-semiconductor field-effect transistors when cycled from inversion to accumulation,” J. Appl. Phys., vol. 71, no. 4, pp. 2028
–2029, Feb. 15, 1992
"lowest ever noise in e- within their speed and power budget" - how sure are you that they will be able to squeeze to the lowest possible noise in e-/given speed and power? If I tell 10 designers to design a readout channel, I am sure they all will come back different noise numbers/given speed and power. And the designers who do not know that I have set extremely high e-to-v CG in my pixel do the best job in designing that readout channel. You are assuming an ideal case, while we are talking about real people publishing real work.
ReplyDeleteThat is why - bumping up the pixel CG gain gives you a leeway and relaxes the constraints in such a way that people start to forget about the optimization needed in the analog channel.
"how sure are you that they will be able to squeeze to the lowest possible noise in e-/given speed and power"
DeleteDid I say they got the lowest possible noise? Please read again please.
They did, as per the graph in Alberts' report, reach the lowest noise in e- ever.
"in such a way that people start to forget about the optimization needed "
You are making assumptions here. Perhaps there is more room for improvement, maybe there is not. As I said, it is possible they called it a day when they got the lowest noise in e- ever reported within their speed and power budget. That doesn't mean that they "forgot" about anything.
Bumping up the CG gives you leeway to achieve the same e- noise with lower power, but because you (and your competitors) have access to technology with higher CG, the market will expect you to lower power at the same noise, or keep power at lower noise.
Of course different designers will do better at optimizing the trade-off, but any good analog designer does not "forget" about such obviously needed optimizations.
-wismerhill
If you go for the lowest noise possible, independent of any other parameter, then every single micro-volt of noise counts, the one in the readout channel maybe less that the others, but you should "fight" for every single micro-volt. And that makes the work of those who go for the electrons as challenging as the work of those who go for the micro-volts.
ReplyDeleteAlbert, your achievement of 30uV noise from SF is great and it's far better than any actual design. Could you please give some hints on this performance please? Thanks!!!
DeleteSee my literature list on www.harvestimaging.com/publications.php and check for the work of Yue Chen, especially nr. 178.
DeleteThere are two main technologies applied : buried channel SF to lower noise in general and 1/f in particilar, and correlated multiple sampling with column-level ADC based on digital counters with BWI.
Thanks Albert!
DeleteAnother question: how to compare slow amplifier with single sampling and fast amplifier with multiple sampling?
-slow amplifier with high capacitive load=high area
Delete-fast amplifier with multiple sampling ADC=much higher power consumption.
You are better off using multiple sampling through analog integrators or by using sigma delta ADC