Thursday, March 23, 2017

ST SPAD Presentation

ST kindly permitted me to publish few slides from Bruce Rae presentation "Fully industrialised Foundry SPAD in an optimised 130nm CMOS imaging technology" at Image Sensors Europe in London, UK, on March 15, 2017:

Update: ST asked me to add a following statement:

"STM adds SPADs to its CIS foundry business in addition to its advanced CIS processes and pixels. STM is now enriching its CIS foundry offer with access to its 130nm CMOS SPAD technology. The fully industrialized SPAD pixel and associated IPs, shipped in more than 250 Million of STM’s FlightSenseTM technology based products, is now available to STM customers under a foundry business model. Customers can now benefit from more than 10 years of R&D, as well as a proven, reliable, high volume capable supply chain. Regular MPW shuttles are planned, starting in Sept 2017."

7 comments:

  1. I think the key part in SPAD is circuit design, not process. Am I right?

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  2. Its pretty much the SPAD itself, process cleanliness, choice of device structure, diode size, shape, capacitance, use of STI or DTI, use of poly or not.

    The AQAR circuit is part of the performance, allowing faster recharge and lower dead time etc, however even if the circuit can recharge the SPAD for a dead time <5ns, the SPAD may produce higher after-pulsing in such situations.

    The choice of circuit, and array does however impact the fill factor of a SPAD array, but if the n-well to n-well spacing rules are large, and if the SPAD guard ring is also large, then its will be dominated by these. N-well sharing, which is a good route to higher fill factor is of course a structural design rather than circuit design.

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  3. how likely is it to shrink the diode size or increase the fill factor to have larger arrays? Also what is the type of power consumption for this device?

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  4. Very large arrays 90,000 diodes etc have been produced (SPADnet etc). Fill factor is difficult to keep consistent over publications (chip size, pads or not, array only or including processing circuits), however 70% fill factor has been reported.

    The lower the SPAD breakdown voltage, and lower the capacitance the lower its P=fCV^2 power, however realistically its the digital processing you implement and the photon events per second that will dictate power usage.

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  5. Diodes of 5um diameter in a shared N-well have been fabricated.

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  6. curious as to why they report performance at 60 degrees Celsius? at room temperature the DCR would be ~8x less. but to what extent does the afterpulsing become apparent at room temperature?

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  7. The 7ns dead time doesn't match the maximum count rate of 37Mcps.
    Assuming the 7ns, they should reach 1/(e deadtime) = 52Mcps. Assuming the 37Mcps the dead time should be estimated around 10ns. Not a major difference anyway.

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