Saturday, June 17, 2017

High-Speed Low-Noise Column ADC Architectures Thesis

Shizuoka University, Japan, publishes PhD Thesis "A Study on High-Speed Low-Noise Readout Architectures and Column A/D Converters for CMOS Image Sensors" by Tongxi Wang. The thesis starts with a nice overview of the readout and column-parallel ADC concepts:


A Hybrid Tri-Stage-Pipeline Column ADC (TSP) architecture is proposed to achieve the better trade-offs (implemented in 65nm process):


Another proposal is Folding-Integration/Cyclic Cascaded ADC (FICC) (implemented in 110nm process):

1 comment:

  1. Do not agree much with the table showing the speed of different ADC architectures. SS is unbeatable at <=10bits, DS is unbeatable at >=13bits. Yet, both are listed as low speed.

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