Wednesday, October 31, 2018

Imec High Speed Imager

MDPI piblishes Imec paper "Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification" by Linkun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, and Jonathan Borremans.

"This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−."

7 comments:

  1. http://www.freepatentsonline.com/6097022.pdf

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    1. May be expired by now, like most of the early CMOS image sensor patents.

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    2. But this is the same principle in a parametric amplification used since long time in micro-wave amplification ... by using a Varicap.

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    3. If this is the same principle then literally nothing anybody is publishing these days should be published. We just stop sharing anything and cancel all conferences, journals etc... The patent that is brought up here cycles the gain of the SF and is admittedly an interesting thing to do. The paper cycles an intermediate transistor before a memory bank to yield acceptable noise while shrinking unit caps of a memory bank. It is still an interesting read and I see absolutely no reason to talk this down. Also the paper does not claim to have invented the idea of cycling the gain of moscaps by cycling between inversion and accumulation. Hence, I think these comments are unnecessary. We're all just using diodes and transistors and operate them with fix or changing bias. If we look at it like that nothing we do is worth publishing. But then there's also no point in arguing about it...

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  2. Well said... fully agree! This content is still much more meaningful than the recent NIT YouTube videos ;)

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  3. Well said indeed!

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  4. Thanks for reminding me that my comment was indeed misleading. The comment is only on the patent claim which generalizes the MOSFET to a electrically variable capacitance. Obviously the paper is very interesting and inspiring.

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