Sunday, August 31, 2008

How to Conceal Image Lag

Many 4T pixel designers are forced to make a difficult trade-off between full well, dark current and image lag. The bigger full well, the lower dark current, the larger image lag grows. Small pixel size makes these trade-offs extremely painful, as virtually any combination sacrifices image quality in one way or another.

In that respect it's interesting to look on Micron's patent US7417677, published just a few days ago. Its main idea is to combine a regular readout with a full discharge of the photodiode - see the pictures below:




After the photodiode charge is read, a low voltage, for example, ground, is applied to the floating diffusion and the photodiode. Essentially, the photodiode is charged to its full well or so. Then the photodiode is reset again to high voltage by the usual readout sequence. So the history is mostly deleted, sans a slow trapped charge which needs long time to wipe out.

What we get in the end? All the conventional image lag measurements, such as one described in Nokia-ST SMIA standard, would show very small image lag, if any. This is great, everybody knows that image lag is a thing to avoid.

What we lose? We totally distort low-light linearity in comparison with "true" lag-free sensor. Best case, the small signal would be reduced to even smaller one, much out of proportion. Worst case, the small signal would virtually disappear. However, the small signal linearity is tricky to measure. And for some reason, SMIA allows not to measure linearity below 10% of full scale.

So, using this idea, one ends up with a great looking spec, but bad real world low-light performance. Probably, low-light linearity data should complement the image lag number to give a true understanding of sensor behavior.

Update: Just because there exists a patent does not mean it is used by Micron, or used in the manner described.

5 comments:

  1. This operation just ensures that if charge is not completely transferred (as it is intended to be with a junction photogate aka pinned photodiode) that at least it is the same each time. It also ensures that any traps are refilled each cycle, not unlike a "fat zero" in the CCD days.
    Without complete charge transfer, there is always leftover kTC noise (except it is not kTC noise).
    Lastly, just because there exists a patent does not mean it is used, or used in the manner described.
    Anyway, I am sorry to tell you that I believe your comments are incorrect.
    -EF

    ReplyDelete
  2. You are right that leftover charge is the same each time and the traps are partially refilled. And there is some "non-kTC-noise" added.

    However, I'm saying something different - the small signal disappears, or, at least, becomes much smaller and non-linear. For a color sensor non-linearity means that low-light colors are garbled.

    This is fundamentally opposite from CCD fat zero, which improves small signal transfer.

    ReplyDelete
  3. Hmmm, I think it depends what problem exists in the sensor. If one can keep the traps filled then small photosignals are not trapped and come out on the first transfer. That is like the CCD case. This assumes that aside from traps, the 4T is designed to yield complete charge transfer.
    If the 4T is improperly designed or clocked so that some charge is always left behind, then small signals should still be skimmed on readout but with noise.
    It could be that your experience with sensors is different and some other sort of problem exists that would lead to small signal distortion.
    Anyway, it is a stretch to say that because of the patent you cited which may or may not be in use by Aptina, that Aptina might not be representing the true low light performance of their sensors. It was this (spurious, I think) conclusion that got my attention.
    If you know that Aptina's low light color performance is "garbled" and that this is the reason, then I stand corrected.
    -EF

    ReplyDelete
  4. Usually 4T pixel transfer gate traps do not dominate in the image lag. Not in processes that I've seen, anyway. But even if they do, a good portion of traps needs a long time to catch electron and then a long time pass to release it. For many types of traps these two times are of the same order of magnitude. So, filling the transfer gate channel by free electrons for few microseconds and then starting the integration for few ms or longer does not guarantee that upon completion of the integration time the traps remain filled. So the readout process would deal with empty traps again.

    This is different from fat zero in CCD where free carriers of the fat zero co-exist with signal carriers at the same time. So the traps are filled by fat zero and the signal comes on top of that.

    In modern small 4T pixels most of the image lag comes from a charge pocket between PD and TG. Sometimes the PD pinning cuts an isolated portion of PD, so the charge there does not have a path to TG. When pixel is small and with all the process variations and misalignments and a full well challenge and a dark current challenge, image lag is often sacrificed as a less important parameter.

    Anyway, my post does not say that the patent is in use by Aptina. Neither it says that Aptina's low-light colors are worse than others. To clarify this I'm adding such a note in the post.

    ReplyDelete
  5. Just one minor correction to what I wrote: the transfer gate traps are a distribution of fast and slow traps. Fast traps have shorter time constant in capturing and releasing carriers, while slow traps are slower in that. The patent does not help in filling either of them when it comes to the readout phase.

    ReplyDelete

All comments are moderated to avoid spam.