Image Sensors on ISSCC 2009

ISSCC 2009 program just has been published (even though the page is still empty, clicking on "Press" drop down menu and choosing "Advanced Program" works). This year one of the pre-conference forums is devoted to Medical Image Sensors, quite interesting stuff.

There are many interesting ideas to be presented on the Imagers session. The most interesting to me is Toshiba 8MP sensor.

A 1/2.5-inch 8Mpixel CMOS Image Sensor with a Staggered Shared-Pixel Architecture and an FD-Boost Operation

N. Tanaka, J. Naruse, A. Mori, R. Okamoto, H. Yamashita, M. Monoi
Toshiba Semiconductor, Yokohama, Japan

A 1/2.5-inch 8Mpixel CMOS image sensor employs a staggered shared-pixel architecture to suppress Gr/Gb sensitivity imbalance. It also employs an FD-boost operation using the Cgs and Cgd of amplifier transistors to yield large FD capability and low dark random noise. It achieves a Gr/Gb sensitivity ratio of 99.7%, random noise of 2.6erms and a pixel capacity of 7.7ke-.

Now, when Toshiba says it, FD boost idea seems quite natural one to use. I have not heard anybody used it though.

Canon presents an interesting sensor, probably for camcorder applications:

A 1/3.2-inch 3.3Mpixel CMOS Image Sensor with a Column-Signal-Addition Method Using a PMOS Column Amplifier

H. Takahashi, T. Itano, T. Watanabe, K. Iwata, H. Akabori, S. Takimoto, R. Mishima, I. Ueno, K. Sakurai, T. Ichikawa, G. Momma, S. Inoue
Canon, Ayase, Japan

A 1/3.2-inch 3.3Mpixel CMOS image sensor is fabricated in a 0.15μm 1P3M CMOS process. A deep-photodiode-isolation pixel and PMOS column amplifier achieves 96μV/e- conversion gain, 7.2e-/s dark current at 60°C, and 2.5erms random noise. The sensor has a column-level signal-addition mode that realizes 15500e-/lx·s sensitivity (green pixel) and interlace scan.

Sanyo surprised me with its CMOS sensor for niche applications. I thought Sanyo has stopped developments of new image sensors, but it looks I was wrong:

A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging

R. Shimizu, M. Arimoto, H. Nakashima, K. Misawa, K. Suzuki, T. Ohno, Y. Nose, K. Watanabe, T. Ohyama, K. Tani
Sanyo Electric, Anpachi, Japan

A CIF-format charge-multiplication 0.35μm 2P4M CMOS image sensor with 10μm pixel pitch is presented. It can execute charge multiplication using impact ionization of photo-generated signals within each pixel. For a significant increase in SNR at low light levels, up to 60× charge multiplication is achieved at a readout speed of 100μs/frame.

Once we are at video applications, Aptina presents its high DR VGA sensor with very impressive spec:

A Dual-Conversion-Gain Video Sensor with Dewarping and Overlay on a Single Chip

A. R. Huggett, C. Silsby, S. Cami, J. Beck
Aptina Imaging

A 47mm2 video sensor SoC comprises a 60fps 640×480 array of dual-conversion-gain 5.6μm pixels with >80dB DR, noise floor of <1erms and switchable sensitivities of 2.5V/lx·s or 11.9V/lx·s
and corresponding PRNUs of 0.57% or 0.68%, a video processor for correcting optical warp of up to 96 lines together with perspective adjustment, and a video overlay circuit.

Another interesting design is fashionable 3D-stacked sensor:

A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor

V. Suntharalingam, R. Berger, S. Clark, J. Knecht, A. Messier, K. Newcomb, D. Rathman, R. Slattery, A. Soares, C. Stevenson, K. Warner, D. Young, L. Ang, B. Mansoorian, D. Shaver
MIT Lincoln Laboratory, Lexington, MA
Irvine Sensors, Costa Mesa, CA
Forza Silicon, Pasadena, CA

A 3D-integrated back-illuminated 1Mpixel CMOS image sensor tile includes a stack of 2×32-channel vertically integrated ADC chips, and requires 13.4μm of silicon perimeter to the pixel array. The tile and system connector design supports 4-side abuttability and burst data rates of 1Mpixel in 1ms.

Another interesting paper talks about column-parallel cyclic ADC:

A 0.1e- Vertical FPN 4.7e- Read Noise 71dB DR CMOS Image Sensor with 13b Column-Parallel Single-Ended Cyclic ADCs

J. Park, S. Aoyama, T. Watanabe, T. Akahori, T. Kosugi, K. Isobe, Y. Kaneko, Z. Liu, K. Muramatsu, T. Matsuyama, S. Kawahito
Brookman Lab, Hamamatsu, Japan; Shizuoka University, Hamamatsu, Japan

A CIS with 13b column-parallel cyclic ADCs is presented. A single-ended architecture with low read noise increases DR up to 71dB. A vertical FPN of 0.1erms is attained using digital CDS, which performs A/D conversion twice in a horizontal scan period of 6.83μs. The imager has 7.07V/lx·s sensitivity, 5.6μm ADC pitch, 61μV/e- conversion gain, 4.7erms read noise and <0.5 LSB DNL

I was expecting more papers on consumer low-cost BSI sensors and small pixels, but this year ISSCC seems to omit these themes - quite strange, considering the huge efforts that industry is spending on this stuff.