Albert Wang (Cornell University) "An Angle Sensitive CMOS imager for single-sensor 3D photography"
Robert Johansson (Aptina) "A 1/13-inch 30fps VGA SoC CMOS image sensor with shared reset and transfer gate pixel control"
Sangjoo Lee (Samsung) "A 1/2.33-inch 14.6M 1.4 um pixel backside illuminated CMOS imager sensor with floating diffusion boosting"
Dan Pates (Aptina) "An APS-C format 14b digital CMOS image sensor with a dynamic response pixel"
Takayuki Toyama (Sony) "A 17.7 Mpixel 120 fps CMOS image sensor with 34.8 Gb/s readout" - this is probably the same sensor that Sony talked about last week, so I'll quote Albert's impressions from the presentation:
"The sensor reported was on based on the “classical” Sony concept of column parallel ADCs based on up-down counters. But because of the extremely high bitrate of the overall chip, the 14 counters in the column are split into two parts:
- The lower 5 bit counters, which are driven with 248 columns in parallel, in such a way that the columns do not contain the real counters, but contain memory cells,
- The upper 9 bit counters, which are based on real counters as before.
This hybrid construction allows to maintain the high accuracy of 14 bits with the extremely high speed of 34.8 Gb/s overall. The device runs at 120 fps at 12 bits and 60 fps at 14 bits. The chip is realized in 90 nm technology, 1P4M and consumes a total power of 3W at 120 fps."