Image Sensors at 2011 VLSI Symposium

2011 Symposia on VLSI Technology and Circuits to be held on June 13-17 in Kyoto, Japan has published their advance programs with abstracts of few papers on image sensors:

A Digital CDS Scheme on Fully Column-Inline TDC Architecture for An APS-C Format CMOS Image Sensor
T. Takahashi, H. Ui, N. Takatori, S. Sanada, T. Hamamoto, H. Nakayama, Y. Moriyama, M. Akahide, T. Ueno and N. Fukushima
Sony Corporation and Sony LSI Design, Japan

This paper proposes a digital correlate double sampling (CDS) scheme which is suitable for a column-inline time to digital converter (TDC). The column-parallel TDCs, where measurements are made with a counter and delay line interpolation, achieve high speed A/D conversion without decreasing resolution. An APS-C format image sensor with 12-bit 360 Mpixel/s readout is realized in a cost-effective 0.18-µm CMOS technology.

A 640×480 Image Sensor with Unified Pixel Architecture for 2D/3D Imaging in 0.11μm CMOS
S.-J. Kim, J.D.K. Kim, S.-W. Han, B. Kang, K. Lee and C.-Y. Kim
Samsung Advanced Institute of Technology, Korea

A 3D image sensor is presented employing a time multiplexed concept for color and depth image acquisition in a single chip to generate a real-time 3D image of an arbitrary scene. The pixel adopts a split photodiode to demodulate time-of-flight signals effectively. Every four pixels share two storages and readout transistors to utilize 100% of photons and increase the sensitivity of infrared light by simple binning operation at the expense of resolution. With the fabricated prototype sensor, 640x480 color and depth images of the scenes 1-3m away are captured with an accuracy of 1-6cm.

A Dual In-Pixel Memory CMOS Image Sensor for Computation Photography
G. Wan, X. Li, G. Agranov, M. Levoy, and M. Horowitz
Aptina and Stanford University, USA

We present a new image sensor to help applications like high-dynamic range, structured illumination, motion corrected photography, etc. by providing two analog memories in each pixel. Clever pixel design allowed us to create the smallest pixel size and the largest fill factor for this class of imager, while supporting dual global shutter operation and true correlated double sampling (CDS) readout from both in-pixel memories to cancel kTC noise.

A CMOS Σ-Δ Photodetector Array for Bioluminescence-Based DNA Sequencing
R.R. Singh, B. Li, A. Elligton and A. Hassibi
University of Texas at Austin, USA

A fully-integrated photodetector array for long-read length bioluminescence-based DNA sequence-by-synthesis is implemented. Each pixel has 120dB photocurrent detection dynamic range and includes a 10fA-10nA pulse frequency modulation (PFM) background subtraction block and a 1st-order Σ-Δ modulator.

Electronic Global Shutter CMOS Image Sensor Using Oxide Semiconductor FET with Extremely Low Off-State Current
T. Aoki, M. Ikeda, M. Kozuma, H. Tamura, Y. Kurokawa, T. Ikeda, Y. Endo, T. Maruyama, N. Matsumoto, Y. Ieda, A. Isobe, J. Koyama and S. Yamazaki
Semiconductor Energy Laboratory, Japan

A novel CMOS image sensor including a pixel with a hybrid structure of an oxide semiconductor FET (OS-FET) and Si(SOI)-FETs has been developed. The OS-FET has an extremely low off-state current, and thus can form a highly insulating charge storage node in combination with SOI. We have therefore applied the OS-FET to an electronic global shutter CMOS image sensor and confirmed improvement in imaging quality.