Tuesday, February 28, 2012

ISSCC Report, Part 4: Cyclic and ΣΔ ADCs

Albert Theuwissen published the fourth part of his ISSCC review. This part covers different ADC architectures coming from NHK, Samsung and Delft University.

7 comments:

  1. I think the samsung APS-C image sensor is similar to the paper of Shizuoka Univ at ISSCC2011.

    Does any guys know details? This paper has few information.

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  2. Do you mean that they copied thier idea as usual?

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  3. @ "The ADC is based on an up-counter with BWI (Bit-Wise-Inversion) to allow digital CDS."

    I'm not at the conference and haven't read the paper, but does this digital CDS involve counting up in a twos' complement representation for the reset level, then loading the complement into the counter and continuing to count up for the signal level?

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    1. Something like that yes, after counting up for the reset level (multiple times if needed), all bits are inverted and basically the result is made negative. Then you start counting up again for the actual video level (multiple times if needed). At the end of the road, you simply devide the end result by the number of oversamplings. That's it. Sometimes live can be easy, sometimes !

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  4. Dear Albert, thank you very much for the useful report from ISSCC! In the comment of the paper of your student you said that the performance can still be improved and the readout noise can fall below 0.7e. However, I remember that last year the sub/electron noise papers mentioned that the limitation for further noise reduction is the 1/f noise. Did your student use special tricks to solve that? Is the 1/f noise somehow related to the conversion gain?

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    1. The 1/f in our testdevice was kept down by means of the buried channel source follower.

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