News and discussions about image sensors
If it is fully depleted, I would assume that backside passivation is extremely important?
Hi there,No backside passivation is required in case holes are used as signal charges. The reason is that the positive charge in the oxide layer (thin brown layer in the image) surrounding the silicon forms an inversion or accumulation layer of electrons at the oxide silicon interface. This layer of electrons prevents hole generation at the interface which would otherwise increase the dark current noise considerably.Another benefit of the inversion / accumulation layer is also that there is always a strong electric field pushing the holes away from the interface and therefore hardly any signal charge trapping will be present at the interface.In case you want to study the effect of an inversion / accumulation layer on the interface leakage current you can check for Multi Pinned Phase (MPP) operation in CDDs which can reduce the dark current generation rate by upto two orders of magnitude.To summarize very low dark current generation and signal charge trapping rates can be achieved despite the lack of any backside passivation.
Very well, it was not very apparent that you were using n-type substrate material. How can this be standard CMOS compatible?
Hi,In case the substrate interface in the pixels comprises an inversion layer such substrate material is obviously p type enabling CMOS compatibility. However, in case the substrate interface in the pixels comprises an accumulation layer such substrate material must naturally be n type. The n type substrate material in the pixel matrix could be an n type well in an otherwise p type wafer. Alternatively, the wafer could be n type but outside the pixel matrix a p type well would be provided for the CMOS electronics. One should note that neither standard implants before and during a CMOS process nor well drive-ins before the start of a CMOS process do not considerably affect the CMOS manufacturing process. However, in order to maintain similar device operation doping profiles in and around existing CMOS devices should be kept similar so that CMOS compatibility is sustained.
The video didn't say anything about read-speed. Is this something that can scale up easily to 8K at 120FPS?
Hi Jay,In case source follower read-out is used in the 1T MIG pixel the read-out speed of a single pixel is similar to normal CMOS. However, since the 1T MIG pixel array is back-side illuminated and it can be manufactured with a standard CMOS process comprising typically much more metal layers than a normal CMOS image sensor process one can divide the array into stripes which can be read-out simultaneously increasing considerably the read-out speed. In this approach the source lines would probably need to be shielded so that they would not affect the simultaneous read-out of pixels in other stripes but this should not be a too difficult task.Another way to enhance the read-out speed is to use current mode read-out. The benefit of the current mode read-out is that one does not need to constantly charge and discharge the source line capacitance increasing the read-out speed and reducing the power consumption substantially. A nice benefit of the current mode read-out is also that since the potentials in the source and drain lines are kept essentially constant one does not need to shield the source or drain lines in case the pixel matrix is divided into stripes with separated read-outs.By combining the back-side illumination, the many available metal layers of a standard CMOS process, as well as current mode read-out one could increase the read-out speed by one to two orders of magnitude while still keeping the power consumption at an acceptable level.The ultimate solution would naturally be to bond imager and read-out chips on top of each others since in this manner a large number of stripes (of the pixel matrix) could be individually bonded to corresponding read-out electronics enabling massive parallel processing of the image data.It is important to note that the 1T MIG pixel suites better for current mode read-out than the present CMOS pixels since multiple CDS samples can be taken at different current levels by just adjusting the gate voltage, i.e., one can take e.g. 2 or 3 current samples with different gate voltages before as well as after reset. The precondition for this is that a deep buried channel is used and that the gate oxide interface is kept fully depleted also during reset. In this manner the interface traps below the gate are not charged and therefore the subtracted read-outs can be considered as true CDS read-outs. The multiple CDS samples can be used e.g. to optimize the linearity and/or to maximize the dynamic range (this applies naturally also to voltage mode read-out). In order to provide multiple current mode CDS samples in present 4T CMOS pixels one would need, first of all, to use e.g. two to three different source potentials before as well as after the charge transfer. In case a deep buried channel were used interface traps would not be charged or discharged below the gate during this process. However, the different source potentials would change the gate potential due to the source to gate capacitance and therefore interface traps would be charged and discharged in other locations than below the gate hampering substantially the CDS measurements. Secondly, in the 4T CMOS pixel a deep buried channel would reduce the sense capacitance substantially while the parasitic capasitance would not be altered (unlike in the MIG pixel) and therefore the parasitic to total sense node capacitance ratio would increase significantly deteorating the charge conversion gain. Consequently, only one true current mode CDS read-out can be obtained in the 4T CMOS pixel provided that the source potential is kept the same before and after the charge transfer.The DEPFET detector developed by Max Planck Institute is a good example that very accurate current mode read-outs can be performed.
Is there any functional test chip?
We have working single pixel test structures.
any measured data please??
I will publish some measurement results in Pixpolar's web page at the latest tomorrow.
Conversion gain of this pixel should be low if I am not mistaken.
Hi,This is actually not the case. Please find the detailed reasoning below.A large conversion gain is not solely important but instead the combination of large conversion gain and small noise since these two parameters define the read noise. According to first order approximation of the current mode read-out, the conversion gain is the bigger the more the signal charges alter the amount of charge in the channel of the read-out transistor. In other words, the sense capacitance to parasitic capasitance ratio should be maximized.The shared 4T CMOS pixel suffers from a large parasitic sense node capacitance and therefore the sense capacitance should be maximized. In order to achieve this without increasing the read-out transistor size too much a surface channel or very shallow buried channel read-out transistor should be utilized. This would, however, generate a lot of 1/f and RTS noise. In a deep buried channel transistor the 1/f and RTS noise would be naturally mitigated considerably but the sense to parasitic capacitance ratio would be significantly reduced deteoriorating the conversion gain.A big advantage of the MIG pixel is that it offers large sense to parasitic capacitance ratio while still enabling the use of a deep buried channel. This means that the conversion gain can be maximized while the 1/f and RTS noise is minimized which holds true for both current and voltage mode read-out. In the current mode read-out besides maximizing the sense to parasitic capasitance ratio and minimizing the 1/f and RTS noise the read-out current should be as small as possible while still being above a certain minimum value since in this manner the signal to noise ratio is maximized (i.e., the signal charge provides the maximum relative change in the read-out current).As already mentioned in the previous post about the current mode 1T MIG pixel, by taking several samples before as well as after the reset and by subtracting any sample taken before the reset from any sample taken after the reset a CDS read-out can be obtained (assuming that the density of bulk traps having problematic time constants is low at the operating temperature). Consequently, multiple CDS read-out results can be obtained which means that one does not need to care about the threshold variations of the MIG transistors, i.e., in case the current in one of the measurements is too small or too large proper CDS read-out results will still be available. The final measurement result can be a function of all proper CDS read-outs e.g. in order to maximize the linearity, the dynamic range and/or to minimize the noise. Alternatively one could simply minimize the noise by choosing a CDS read-out result with smallest appropriate read-out current value provided that the gate voltage level in the read-outs is the same before and after reset.In a current mode 4T CMOS pixel only one CDS read-out can be obtained meaning that one has to take threshold voltage variations into account by applying a big enough read-out current. In this manner one can guarantee that the read-out current is above the minimum limit in all pixels before and after the charge transfer. The application of such a safety marging in the measurement current increases, however, the noise. In addition, the single CDS measurement capability compromizes the linearity and/or the dynamic range of the pixel.TO BE CONTINUED...
...CONTINUATIONIn voltage mode MIG pixel the deeper the buried channel, the smaller the distance between the MIG doping and the buried channel, and the smaller the MIG doping area, the bigger the conversion gain will be, i.e., the smaller the MIG transistor the bigger the conversion gain. The reason behind this fact is that the size of the parasitic capacitance depends solely on the MIG transistor dimensions, i.e, the parasitic capacitance and the MIG transistor dimensions are always fully coupled.In the voltage mode 4T CMOS pixel part of the parasitic capacitance is independent from the Source Follower Transistor (SFT) dimensions (parasitic capasitance and SFT dimensions are partially decoupled) meaning that at some point the reduction of the SFT size does not increase the conversion gain. This point will be reached first in a deep buried channel SFT and last in a surface channel SFT.It should be noted that maximizing conversion gain typically reduces the full well capacity (which is not that severe in case logarithmic read-out is provided) and increases the channel resistance of the read-out transistor resulting in higher charging and discharging times of the source line and therefore reduces the read-out speed.To summarize, in a voltage mode 1T MIG pixel the conversion gain can be maximized and the noise can be minimized by providing a minimum size MIG transistor with a deep buried channel enabling very small read noise. In a current mode 1T MIG pixel the conversion gain can be maximized and the noise can be minimized by providing a deep buried channel MIG transistor offering multiple CDS read-out capability. On the other hand, in the voltage and current mode 4T CMOS pixels there is always a trade off between the conversion gain and the noise degrading the read-noise. This is due to the trade off between the deep buried channel and the sense to parasitic capacitance ratio. Besides in the current mode 4T CMOS pixel the noise is increased since only one CDS read-out enabled.
Isn't the 4T pixel sense node capacitance = parasitic capacitance??
Hi,The sense node of the 4T CMOS pixel comprises one or more floating diffusions, the source of the reset transistor, the gate of the source follower transistor, and wiring connecting all the previous items together. The actual sense capasitance is the MOS capasitance of the source follower transistor - everything else constitutes the parasitic sense node capasitance.
Artto, what is the typical conversion gain in uV/e-? thanks.
Hi Eric,typical charge conversion gain of a very basic and rather large 10 micron MIG pixel is around 20 uV/e-. As the pixel size is scaled down the conversion gain increases.
Check this out: US 2006/0043520 looks very similar
Hi,This patent application describes a typical Internal Gate (IG) pixel wherein electrons that are collected inside silicon modulate the hole current (or vice versa) of a Field Effect Transistor (FET). In a MIGFET pixel electrons that are collected inside silicon modulate electron current of a FET (or holes modulate hole current). Therefore the MIGFET pixel and the pixel described in the patent application are completely different devices.
One of the key ideas of that patent is that electrons collected in the burred layer are modulating the channel above the collection region. Here is the claim:a channel region located beneath the top surface of the substrate but over said charge accumulation region, said channel region having a resistance characteristic that changes in response to the amount of charge accumulated in said charge accumulation region;
Hi,I don't see a conflict here. First of all, the pixel presented in the patent application combines the benefits of IG and 4T CMOS pixels and as such it is an interesting and novel idea. In an IG pixel signal charges situated below the channel of a FET alter (i.e. reduce) the resistance of the channel. This principle was presented already in 1988 by Jerry Hynecek (Bulk Charge Modulated Device aka BCMD) and even before this by Josef Kemmer and Gerhard Lutz (New detector concepts, 1987). Secondly, the patent application is filed 10 days after the first MIG patent application.
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