News and discussions about image sensors
Parallel clock SerDes outputs are used all the time in CMOS sensors (MIPI CSI anyone?). I think they mean embedded clock SerDes are not currently used.
"SerDes: No Applications in CIS yet?" Wow such a general and albeit incorrect statement mentioned with such a confidence. Only goes to show their ignorance. High Speed SerDes with CDR has been used in CIS for some time. I remember using it even in as far back as 2008.
Simply buy the new SONY GS sensor, all have been made inside.
Not sure the 14-bit single slope is an efficient ADC and generally, single slope are not low power ADCs. Also, Delta Sigma is probably the most power efficient one (Chae et al, JSSC 2011) and has simple and compact analog and digital components. Also, I would have mentioned the cyclic ADC which is also quite efficient in imaging applications (power and/or noise) (Watabe, ISSCC 2012). Apart from this, thanks to Dalsa and the author for sharing..
14-bit = 16384 counts. If you can count at 1Ghz, then the conversion time will be 16us. An CPU can run at 8.8Ghz with complex logic inside, then a simple counter can run at 10Ghz. So 1.6us conversion time is possible.http://valid.canardpc.com/records.php
Good luck with your 1000+ column ADCs, all having 10GHz clock counters ;)
I asked very often if this can be done already. Since with an asynchronous counter, the switching speed decreases fastly.
Don't forget a CPU has a TDP of more than 50W, a large heatsink, fan and system cooling. Not to mention the special cooling that was required to get those overclock records.
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