Sunday, April 26, 2015

VLSI Symposium Preview

VLSI Symposium tipsheet offers a preview of two image sensor papers:

A 3D stacked CMOS Image Sensor with Global-shutter mode and high speed capturing mode:
The paper by Toru Kondo et al. from Olympus Corp. will describe a 16MP 3D stacked CMOS image sensor with pixel level interconnections using 4 million micro bumps. The two semiconductor substrates are bonded by a 7.6um pitch micro-bump array, and the storage node array is comprised on the bottom substrate to improve parasitic light sensitivity (PLS). Both a 16Mpixel global-shutter mode with a -180dB PLS and 2Mpixel 10,000fps high speed image capturing are achieved.


A 3D stacked CMOS Image Sensor with a low noise technique:
The paper by Shang-Fu Yeh, et al., of TSMC will describe an 8Mpixel 3D-stacked low noise CMOS image sensor with Conditional Correlated Multiple Sampling (CCMS) technique. This technique is proposed to solve the low frame rate issue by using multiple small-range voltage ramps. A 0.66e-rms input referred temporal readout noise is obtained with a 5-times CCMS technique, and also both thermal noise and the random telegraph signal (RTS) noise can be
reduced by using CCMS technique.

9 comments:

  1. Is it sure the RTS and 1/f noise are reduced through multiple sampling and not through process optimisation? I've often read that CMS has no effects on these noises

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    1. not completely no effects, but only very limited effects on RTS

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    2. Albert TheuwissenApril 28, 2015 at 1:01 PM

      Normal CDS cancels out a large part of the 1/f noise, but if CMS takes up too much time, 1/f is coming back into play and counteracts part of the noise reduction obtained by CDS. For RTS : CMS can reduce the RTS drastically IF (!!!) an appropriate filtering is applied on the CMS samples.

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  2. My guess is that some data are excluded before the multi-sampling average process.
    -yang ni

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  3. Does anyone know which sort of bonding technology is used for such stacked image sensors? How is it possible to bond chips with 7.6um pitch micro bumps?

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    1. Interesting point. Could you please explain according to you - what are the current limitations?

      Thank you in advance.

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    2. Hi Diko,
      well... I'm not really an expert in this topics but I thought - for 7,6µ bump pitch you'd need something like <1µ placement accuracy and (maybe even more difficult...) also a really high theta accuracy so that all bumps hit their corresponding pad... and then? what can be used to create a reliable interconnect for all of the 4mio bumps? some kind of a TCB kind of soldering process? or is the stack maybe created in a "ziptronix"-type of wafer to wafer bonding?
      however they achieve it - it seems to be an impressive piece of technology...
      - Thomas

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  4. Does anyone know how 7.6um micro-bumping is made possible? micro-bumping at 10-12um I have seen working nicely, but putting 4million bumps at 7.6um is a bit non-yielding from my viewpoint.

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  5. Wow, - 180dB PLS, that is like one in a billion. If the rest is as good and they can realistically implement it, goodbye mechanical shutter :D

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