Computational Imaging Review

Columbia University published Oliver Cossairt's PhD thesis "Tradeoffs and Limits in Computational Imaging" reviewing broad range of modern technologies, such as EDoF, plenoptic cameras, gigapixel cameras, etc. Some conclusions from the thesis:

Figure 1.7: EDOF cameras sacrifice best case performance for average case performance. The performance is measured as the MTF of the camera system as a function of depth.

Figure 2.1: Simulated image performance for three EDOF cameras. An IEEE resolution chart is placed at different depths. The aperture size A and defocus slope in light field space s0 are chosen so that the maximum defocus blur diameter is 100 pixels. The center PSF is used for deblurring, producing the images shown in (b). Close-ups in (c) show that the sharpest image is produced by wavefront coding at the center depth (s0A = 0). However, wavefront coding produces significant deblurring artifacts for defocus values as small as s0A = 33 pixels, while diffusion coding produces near identical results for the entire depth range.

Spectral Focal Sweep EDoF technology is proposed, similar to DxO one, but said to perform better:

Figure 1.9: Performance vs. Complexity for the Spectral Focal Sweep camera (see Chapter 3). A conventional camera achieves higher performance than the Spectral Focal Sweep camera, but at the cost of a significant increase in complexity.

Figure 1.8: Resolution scales rapidly with camera size for ideal diffraction limited lenses. However, in practice, resolution reaches a plateau due to geometric aberrations. The Gigapixel Computational Camera introduced in Chapter 3 breaks the aberration limit so that resolution continues to increase with camera size, despite the presence of geometric aberrations.

Figure 4.6: For conventional lens designs, the F/# typically scales with the cube root of the focal length in millimeters.

Figure 4.11: Scaling laws for computational imaging systems with spherical aberrations. The Rana, which was analytically derived, shows an improvement upon the aberration limited curve Rgeom, without requiring F/# to increase with M. Performance is further improved when natural image priors are taken into account, as the Rprior curve shows. The Rprior curve improves upon the conventional lens design curve Rconv, also without requiring F/# to increase with M.

Samsung Presents 1/3-inch QVGA ToF Sensor

Samsung published Youtube video presenting the new 1/3-inch QVGA ToF Sensor - the S5K32D:



Samsung S5K32D QVGA 1/3" TOF Sensor is said to have high resolution and high speed for Z-axis User Interface. The text abstract also says that it's:

1. World's first QVGA resolution TOF Sensor
2. Supporting high speed frame rate
3. One Chip solution for depth image

Update 2012/02/20: The updated Samsung web site lists 3D ToF part as S5K32A. The pixel uses BSI technology and is of 14um size.

2nd Workshop on CMOS Image Sensors for High Performance Applications

A program has been announced for the 2nd workshop "CMOS Image Sensors for High Performance Applications", co-organized by CNES, Astrium and Thales Alenia Space, to be held on December 6th-7th, 2011 in Toulouse (France). Along these two days, 27 talks about high performances CMOS Image Sensors will be presented by 22 teams from industries, institutes, labs and agencies:

1. Characterization Results of Teledyne-DALSA High Bandwidth Matrix and Linear CMOS Devices and Roadmap for Radiation Hard and High Resolution Area Devices
   COCHRANE David (TELEDYNE-DALSA)
2. High QE, Thinned Backside-Illuminated, 3e- RoN, Fast 700fps, 1760x1760 Pixels Wave-Front Sensor Imager with Highly Parallel Readout
   DOWNING Mark (ESO)
3. Fast-Response, Low-Noise, Multiple Shutter, Non-Destructive Readout Line Sensor for Spectroscopy Applications Based on Lateral-Drift-Field Photodiode Principle
   DURINI Daniel (Fraunhofer Institute)
4. L²CMOS Image Sensor for Low Light Vision
   FEREYRE Pierre (e2v)
5. First Results from Single Photon Avalanche Diodes Manufactured in a 0.18 μm CMOS Image Sensor Technology
   COATH Rebecca (STFC)
6. ESA supported developments in CMOS Imaging Sensors
   NELMS Nick (ESA-ESTEC )
7. Survey of CMOS devices developped by Astrium-ISAE for ESA LEO and GEO missions
   BREART DE BOISANGER Michel (EADS Astrium)
8. Survey of CMOS devices developped by Astrium for Ocean Colour Imaging from GEO
   BREART DE BOISANGER Michel (EADS Astrium)
9. CMOS image sensor for lunar mission
   WANG Weng Lyang ‘Bill’ (CMOS Sensor Inc.)
10. High-Speed BSI CMOS Image Sensor for Space Applications with 1.1Me- Full Well Capacity and 28e- rms Read Noise
    VU Paul (BAE Systems Imaging Solutions)
11. CNES roadmap for CMOS image sensors in Space applications
    MATERNE Alex (CNES)
12. Characterization of a Digital TDI CMOS demonstrator
    LEPAGE Gérald (CMOSIS)
13. Monolithic, 120 mm CMOS sensor for Multi-mode RSI application
    LO Shih-Hung ‘Redman’ (NSPO)
14. Developments of back side illuminated CMOS APS for EUV Solar Observations
    BENMOUSSA Ali (STCE Royal Observatory of Belgium)
15. Digital Focal Plane arrays for Cooled Infrared Detectors
    DECAENS Gilbert (SOFRADIR)
16. IR Sensors for space applications at Selex Galileo
    WELLER Harald (SELEX GALILEO)
17. Innovative ROIC for very low flux sensors
    SANSON Eric (SOFRADIR)
18. Specifications of an Analog-to-Digital Converter For uncooled infrared readout circuits.
    ROBERT Patrick (ULIS)
19. CTIA circuit for low light level imaging with InGaAs detector.Demonstration with a 15μm pitch VGA format
    GUELLEC Fabrice (CEA-LETI)
20. A 2 photon noise 2 KHz frame rate, with in-pixel CDS, IR sensor for Adaptative Optic Applications
    SALVETTI Frédéric (SOFRADIR)
21. Optimisation of performance of Backthinned CMOS devices
    JERRAM Paul (e2v)
22. Results of the second generation hybrid backside illuminated imagers and an introduction to other high-end imager developments at imec
    MINOGLOU Kiki (IMEC)
23. Outstanding properties of Espros Photonic CMOS process for high performance imaging
    POPP Martin (Espros Photonics AG)
24. A Common Gate Pinned Photodiode Pixel
    DE WIT Yannick (ON Semiconductor)
25. Reduction of pixel 1/F noise by inversion/accumulation cycling
    DUPONT Benoît (CAELESTE)
26. Radiation Effects on CMOS Image Sensors
    VIRMONTOIS Cedric (ISAE)
27. Performance of deep submicron CMOS image sensors after radiation
    BERNARD Marie (CNES)

The workshop is free of charge. One can register here: http://cnes.cborg.net/cct/bipublicgb.html

Thanks to AT for sending me the program!

Yole Predicts 75um Thin CIS Wafers in 2014

Yole Développement's report "Thin Wafer Market & Applications" predicts that thinned wafers will reach 50% of all wafer shipments in 2016, up from 27% today. "Motivations for thin wafers are: high interconnect density (such as aggressive TSV pitch & diameters), better power dissipation and higher electrical performance and reduced package size."

Here is how image sensor wafer thickness looks in comparison with others:

Small Pixels and Machine Vision

Adimec blog published a post on small pixel potential in machine vision applications: "Can small pixel CMOS image sensors be useful in Machine Vision?"

The conclusion is: "There is a trend towards using smaller pixels for machine vision applications leveraging technology developed for the high volume consumer camera applications. However the requirements for machine vision are very different and it will take some time before the image sensor pixels have high enough performance to make it into the machine vision cameras."

Oppenheimer Research Speculates that Omnivision is Inside iPhone 4S

Oppenheimer Research note states that Omivision is likely inside the newly announced iPhone 4S. The #1 reason is:

"Apple in its iPhone release presentation mentioned that the image sensor is a 8MP sensor with the description 3264 pixels X 2448 pixels resolution or 7.99MP. It is spot on with OVTI's 8830 spec, whereas Sony's 8MP spec is 3288 X 2472 or 8.12MP."

Update: More analyst's speculations:

Barrons: R.W. Baird’s Tristan Gerra writes that his “field research” suggests Omnivision has lost some share to Sony in the 4S, citing anecdotal evidence that the Sony part matches the phone’s specs.

“Various websites report these Sony Ericsson smartphones feature a Sony image sensor of the exact size as for the iPhone 4S (3264×2448),” he writes, adding, “Additionally, image sensor makers typically customize their sensors specifically for Apple without necessarily releasing the specs.”

But JP Morgan’s Paul Coster comes to the stock’s defense, noting that Apple describes an a larger “active array size” to the iPhone’s sensor. That, he suggests, implies the phone uses OmniVision’s “OVT8830 CIS” chip. “The iPhone 4s sensor active array was announced to be 3264 by 2448, which is an exact match for the Omnivision OVT8830 first-generation BSI image sensor,” writes Coster, “We note that Sony’s IMX105PQ 8MPx chip has a 3288 by 2472 array.”

Motley Fool writes, again relying mostly on the sensor format: "I think I've built a pretty compelling case here for the OV8830. Dual-sourcing a component this important just doesn't fit Apple's modus operandi."

Brookman Technology Presentation

Youtube video from few months ago shows Brookman Technology presentation, including a short company story, a talk about 1.3MP/2000fps fast sensor with global shutter and 5.6um pixels, and sub-electron noise 16b DR sensor with 7.5um pixels demoed at 0.03 lux/F1.4/10fps:

Chipworks Reverse Engineers CMOSIS Sensor

Chipworks published CMOSIS fast 4MP/180fps CMV4000 reverse engineering. The sensor features fully pipelined global shutter. The report covers the imager process.

It's Official Now: Nobukazu Teranishi Received 2011 PSA Progress Medal

For some odd reason, there was no official news report on the award. Now there is - Photographic Society of America Fall Newsletter has an article on Nobukazu Teranishi receiving 2011 PSA Progress Medal Nobukazu Teranishi at the Final Banquet of the 73rd Annual Conference of Photography held in Colorado Springs, Colorado.

Nobukazu Teranishiis the General Manager in the Image Sensor Business Unit in Japan. He has been an influential technical leader in the development of both CCDs and CMOS sensors for 31 years, and accomplished the following three key technologies:

1. the pinned photodiode for no image lag, low noise and low dark current
2. technologies to prevent high light deterations
3. mega –pixel technologies for HDTV cameras and digital still cameras.

Almost all CCD’s and CMOS sensors use pinned photodiodes now and 200 million CCD’s and one billion CMOS sensors were produced in 2008.

Invisage Reveals Few More Bits of its Technology

Invisage patent applications US20110228144 and US20110226934 have been published. The US20110228144 is titled "DARK CURRENT REDUCTION IN IMAGE SENSORS VIA DYNAMIC ELECTRICAL BIASING" and shows how Invisage plans to reduce sense node diffusion dark current in what looks like a typical 3T pixel:

Invisage approach is quite simple - precharge the sense node to zero voltage so that in the dark the sense node voltage is always zero. Here is the timing diagram and the description (I used slightly wrong pixel figure because it has better labeling. The photocurrent direction is wrong):

"During a first period labeled “True reset,” the diode, or charge store, is reset to a known reference point, by setting the reset electrode to high voltage (turning on the reset transistor M1). In embodiments, during the reset phase, the electrode vfilm (i.e., the biasing electrode) is set to a bias voltage that is higher than diode voltage, for example 3V (normal range from −5V to 5V). The pixel electrode diode is driven to be a lower voltage, for example 0V (normal range from 0V to 5V). This is achieved by setting VLEVEL to a low voltage.

During a second period labeled “Integration,” the electrode vfilm remains at the same voltage, for example 3V. Light induced photocurrent in the floating photodetector will drive the diode voltage higher. The photocurrent serves as a current source in this configuration. The use of a low voltage on the pixel electrode significantly suppresses the dark current of the pixel circuitry under a dark condition. VLEVEL is pulled back to high voltage such as 3V, to minimize leakage path of transistor M1, and to prepare for readout phase.

During a third period labeled “Read signal,” the electrode vfilm is brought to a higher level, such as 5V (normal range −5V to 5V). This will boost up the diode voltage to make sure the low voltage at diode node can be read out through the readout circuit, and thus maintain dynamic range for the readout path. Alternatively, a low VT readout transistor M2 (for example, threshold of 0V, with range of −1V to 1V) can be used to read out the low voltage, in which case the pulsing on common electrode is not necessary.

During a fourth period labeled “CDS reset,” the reset electrode goes high again, setting the diode voltage to the same known level. This is achieved by pulling VLEVEL to the same low voltage as in ‘true reset’ phase.

During a fifth period labeled “Read reset,” VLEVEL is pulled back high to allow M2 functions as a readout transistor. This phase is used to readout the reset level."

The idea is quite nice but what about Reset transistor M1 charge ingection variations due to pixel-to-pixel mismatch? One can not allow sense node to go negative, so the average sense node voltage should be high enough to keep worst case pixel in positive domain. This can easily be 50mV or so for the average pixel. At this voltage the dark current would be lower, but not zero.