CIS Content on 2007 VLSI Symposium

Image sensor content on 2007 VLSI Symposium in not that large.

As one could guess, Samsung will present 1.4um pixel paper:

Dedicated Process Architecture and the Characteristics of 1.4 μm Pixel CMOS Image Sensor with 8M Density

A 1.4um-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

For the first time TI makes public its work in image sensors (other than Impactrons and more regular CCDs):

A 200-μV/e- CMOS Image Sensor with 100-ke- Full Well Capacity

A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-um 2P3M process achieves 200-uV/e- conversion gain with 100-ke- full well capacity, 2.2-e-rms noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.

As it sounds from the abstract, TI's idea is limited to non-shared 4T pixels. If true, its pixel size scalability is poor, relegating it to security, automotive and other niche markets.