A Leading-Edge 0.9μm Pixel CMOS Image Sensor Technology with Backside Illumination: Future Challenges for Pixel Scaling (Invited)
S.G. Wuu, C.C. Wang, B.C. Hseih, Y.L. Tu, C.H. Tseng, T.H. Hsu, R.S. Hsiao, S. Takahashi, R.J. Lin, C.S. Tsai, Y.P. Chao, K.Y. Chou, P.S. Chou, H.Y. Tu, F. L. Hsueh, L. Tran,
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, R.O.C.
Some interesting quotes from the paper talking about the new N65 300mm BSI process performance:
TSMC uses "Backside antireflection (BARC) layers
"wafer-to-wafer ... average thickness variation (are) within 3% of the mean value. ...within-wafer TTV (total thickness variation) for 300mm wafers ... improved to be less than 15%, which is comparable to existing 200mm BSI process as shown in Fig. 3."
One of the problems TSMC observed in small pixels is an increased PRNU level. TSMC team has implemented 4 techniques to improve it:
- tightened design rule with advanced lithography (N45/N28…)
- better pixel-to-pixel isolation
- antireflection film optimization
- novel structure for light guidance
The PRNU-treated pixel shows 7X PRNU reduction for 1.1um pixel and a 4X reduction on the 0.9um pixel:
Crosstalk is another major challenge in small pixel design. TSMC team has identified CFA spectral crosstalk being the dominant component, followed by optical diffraction, and by electrical crosstalk. TSMC calls for novel ideas in color patterning other than traditional Bayer pattern and new system-level color processing algorithm to reduce the CFA spectral crosstalk problem:
Being with Advasense with our high full well pixel claim, I immediately noticed the full well vs pixel size graph, with 0.9um pixel having just ~30% of 1.4um pixel full well:
And finally, there are color sample pictures from the new 1.1um and 0.9um pixels. 0.9um colors looks a bit pale, but this is somewhat expected at this early design stage:
Congratulations to S.G. Wuu and the whole TSMC team! I'm very impressed by your cutting-edge work!