News and discussions about image sensors
What is the shutter efficiency of the new Aptina sensor?
Sony claimed -100dB PLS in their ISSCC'12 paper...
what is the pixel size in this case?
Shutter efficiency is wavelength dependent (at least). It must be specified as a plot vs wavelength otherwise it can be as good as you want. GSE can only be compared when measured in similar test conditions.GSE is also a ratio, a sensor with a 2x less good GSE and a 2x faster readout will actually give the same performance in terms of image quality.
Are there some standard rules in measuring global shutter efficiency?
Arnaud ir right:GSE is a function of wavelength.However, I have never seen anyone reporting GSE like that.Also there is an angle dependence which is not reported either.
Aptina 3.75um vs. Sony 5.86um.
All the interline CCDs are snapshot sensors. Today 4T pixel works like a CCD, so there is no doute that CMOS APS will have snapshot function as good as that in interline CCD. It's only a process issue.
Maybe roughly true but the artifacts are very different in interline CCDs (vertical stripes split between two frames/fields) vs. CMOS (smear trails on individual pixels). This can make a difference in real applications.
Not really. For one thing a BSI CCD global shutter is not going to work well. Second, it is only a process issue in the sense that getting more things into a pixel is a process issue, but really, CMOS requires more stuff per pixel than a CCD so it is harder process issue with CMOS.We have known how to make a global shutter CMOS APS device for a long time, practically coincident with its invention (the intra pixel charge transfer kind). It just has not really been worth the effort since rolling shutter is generally not a big problem. But, perhaps its time has come and there certainly has been some nice recent progress in small GS pixels from Aptina and Sony.
If we use a direct charge storage like in an interline CCD, then the difference between CMOS and CCD is small:CCD: PPD -> VCCD -> HCCD -> FDCMOS: PPD -> MEM -> FDI think that the key process difference is that the CCD is built on thinoxide with very special metal shield which is not yet available in CMOS process. As Dave stated, the smear in CCD is much more troublesome then local leakage in CMOS from application point of view.-yang ni
What do you mean by "thin oxide" ?
Yang, I don't see how you see this difference as "small"! Nor do I see the anti-smear light shield as being the key process difference. But, we don't need to see things the same way!
Interesting discussion here ! First of all, if one technology uses a THIN oxide, then it is CMOS. CCDs use a relative thick gate oxide. But this has not that much to do with the shutter efficiency of smear issue. The main reason why a CCD is doing so much better than CMOS (as far as shutter efficiency is concerned) has to do with the lightshield. The light shield in a CCD is made out of the first metal layer and is nicely surrounding the vertical shift registers along its two side walls and of course on top of the vertical shift register. The CCD light shield is even covering the edges of the PPD. In a CMOS pixel, the first 2 metal layers are used for in-pixel interconnect and the light shield above the storage node is made in metal 3 (for instance). That brings the light shield much further away from the Si interface and makes it much less effective. Hopefully this explanation helps.
Eric, Albert brings the answer to your question. I think that the light shield metal in CCD is not Al, but something more optically opaque. If you take a look at PhD thesis of Markus Loose (so long time ago !!!, he has measured the transmittance of al layer in CMOS. His conclusion was that M1 can only attenuate 2000x and superposition of M1/M2 will not give 2000x2000 attenuation, but onlt 4000X due to some resonance effect. SONY published a paper on their smear reduction for interline CCD by using W light shield. They stated that there are pinholes in the deposited Al layer.Albert, could you please bring more precision on this issue ?-yang ni
but I did not ask any question...! I think maybe it is your question!
What is preventing from having an intermediate metal layer (between active/M1) in CMOS? I have seen some papers/patents on this already
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You need to connect the storage node under the shield, therefore the interconnect must be lower than the shield in the stack.On the other side, it is not 100% true that M3/M4 are the only layers available for shielding. Any free space in M1 and M2 above the storage node can be filled with metal. One of the issue is then the difficulty to control all the parasitic capacitances to properly build the storage node.
How to fill the free space between M1 & M2 with metal please??
Use M3 and M4 please. Of course you cannot use M3 because you run it for control signals, and probably no M4 since you may use it for outputs. Therefore you will have light leaking Floating node!
You can also try using M1 and m2. Keep the minimum distances and minimum metal area and you will soon find that you have what we call "underwear formation"
what means "underwear" formation please??
Not easy to make QE=100%, but it's even harder to make QE=0 haha!
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