Tuesday, September 24, 2013

TSMC Develops Hardmask for Deep Implants

TSMC is going to present its recent developments in hardmask for deep implants in small pixel sensors at NMDC, Taiwan on Oct 6-9, 2013. The paper is titled "Nanotechnology Development for CMOS Image Sensor Applications" by C.C. Wang, T.H. Hsu, S.F. Ting, C.Y. Chen, K.C. Huang, J.C. Liu, S. G. Wuu. TSMC has developed a nice hardmask process for pixel size of order of 1um:

2 comments:

  1. How does this masking working? The implanted area is the masked area???

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  2. Implanted area is the open area- not covered by resist. This would be for photodiode isolation. Tall aspect ratio (if the sidewall is straight) gives a high degree of control over isolation width and thick resist opens up higher implant energies.

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