Friday, September 06, 2013

Fujitsu Announces Milbeaut ISP in SuVolta Process

Fujitsu announces the 7th generation of its Milbeaut ISP, featuring SuVolta DDC low power process. Other than the new process, the ISP features a newly developed circuit for correcting focus drop-off at the edges, an improved distortion correction and purple fringing countermeasures, improved noise filter, has a processing speed of 12fps at 24MP (said to be twice the speed of the previous generation), supports JPEG-HDR, a JPEG-compatible HDR format from Dolby Labs, and can do H.264 encoding/decoding at 1080p30 or 1080i60 rate.

Getting back to SuVolta process, DDC stands for Deeply Depleted Channel transistors and claims to achieve power saving and/or speed-up in more-less standard bulk CMOS techniology:


A 4.5-min long video explains SuVolta's basic claims:

video

The basic claim is a reduction of transistor variability by about a factor of 2:


In theory, these ideas could bring a new life to current-mode image sensors that traditionally suffer from high PRNU due to Gm variations. The regular 3.3V transistors have stddev Gm variations of 1-2% per sq.um area, depending of the fab, process, and device type. Reducing it down to 0.5-1% per sq.um could make current mode pixel more competitive.

For those who have more time, there is also a 3-part lecture in Stanford University introducing DDC technology and comparing it with FinFET and other approaches (part 1, part 2, part 3):



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