VLSI Symposia: Sony Presents Curved Sensor

2014 VLSI Symposia programs have been published with a major image sensor news - Sony is to present its curved image sensor at the Technology Symposium.

2.1 A Novel Curved CMOS Image Sensor Integrated with Imaging System
K. Itonaga, T. Arimura*, K. Matsumoto*, K. Goro**, K. Terahata*, S. Makimoto**, M. Baba*, T. Kai*, S. Bori*, K. Kasahara*, M. Nagano**, M. Kimura**, Y. Kinoshita**, E. Kishida**, T. Baba, S. Baba, Y. Nomura, N. Tanabe, N. Kimizuka and Y. Matoba, Sony R&D Platform, *Sony Semiconductor Oita, **Sony Semiconductor Kumamoto

We realized an ultimately advanced imaging system that comprises a curved, back-illuminated CMOS image sensor (BIS) and integrated lens which doubles the sensitivity at the edge of the image circle and increases the sensitivity at the center of the image circle by a factor of 1.4 with one-fifth lower dark current than that of a planar BIS. Because the lens field curvature aberration was overcome in principle by the curved sensor itself, the curved BIS enables higher system sensitivity through design of a brighter lens with a smaller F number than is possible with a planar BIS. At the same time, we controlled the tensile stress of the BIS chip to produce a curved shape that widens the energy band-gap to obtain a lower dark current. The curved CIS can be applied to an ultimately advanced imaging system that is validated by the evolution of the animal eye in Nature.

Earlier, Sony has applied for a curved sensor patent which might become a base for the new product. Other big news is TSMC presenting its stacked sensor:

21.3 Advanced 1.1um Pixel CMOS Image Sensor with 3D Stacked Architecture
J.C. Liu, D.N. Yaung, J.J. Sze, C.C. Wang, G. Hung, C.J. Wang, T.H. Hsu, R.J. Lin, T.J. Wang, W.D. Wang, H.Y. Cheng, J.S. Lin, C.C. Chuang, S.Y. Chen, C.S. Tsai, Y.L. Tu, S. Takahashi, Y.P. Chao, F.J. shiu and S.G. Wuu, TSMC

This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor performance can be significantly minimized. In addition, for the first time, the degradation of stacked pixel performance during the folded circuit operation under sensor array is found and improved. The final stacked sensor exhibits the comparable pixel performances to conventional BSI. Furthermore, stacked architecture provides the opportunity to enhance sensor performance by the separate process tuning for sensor wafers (without any effect on ASIC wafers), leading to a further improvement of dark performance.

The Circuit Symposium has an image sensor session with 5 presentations:

17.1 A Millimeter-Scale Wireless Imaging System with Continuous Motion Detection and Energy Harvesting
G. Kim, Y. Lee, Z. Foo, P. Pannuto, Y.-S. Kuo, B. Kempke, M. Ghaed, S. Bang, I. Lee, Y. Kim, S. Jeong, P. Dutta, D. Sylvester and D. Blaauw, University of Michigan

We present a 2×4×4mm^3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.

17.2 A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS Image Sensor for Ultra-Low-Power SoCs achieving 40-dB Dynamic Range
D. Bol, G. de Streel, F. Botman, A.K. Lusala and N. Couniot, Université catholique de Louvain

We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.

17.3 An On-chip 72×60 Angle-Sensitive Single Photon Image Sensor Array for Time-resolved 3-D Fluorescence Lifetime Imaging
C. Lee, B. Johnson and A. Molnar, Cornelll University

We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. The pixels use integrated diffraction gratings to extract incident angle, enabling 3-D localization and SPADs to resolve timing information, rejecting high-powered UV stimulus and mapping the lifetimes of different fluorescent sources. The chip
integrates pixel-level counters, and shared timing circuitry, and is implemented in unmodified 180nm CMOS.

17.4 320x240 Oversampled Digital Single Photon Counting Image Sensor
N.A.W. Dutton, L. Parmesan, A.J. Holmes*, L.A. Grant* and R.K. Henderson**, University of Edinburgh / STMicroelectronics Imaging Division, *STMicroelectronics Imaging Division, **University of Edinburgh

A 320x240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.

17.5 A 3.7M-pixel 1300-fps CMOS Image Sensor with 5.0G-Pixel/s High-Speed Readout Circuit
S. Okura, O. Nishikido, Y. Sadanaga, Y. Kosaka, N. Araki, K. Ueda, M. Tachibana and F. Morishita, Renesas Electronics Corporation

A 5.0G-pixel/s readout circuit for 15.3mm×8.6mm optical size, 3.7M-pixel, 1300 fps, and digital output image sensor is presented. To achieve 5.0G-pixel/s readout rate, the high speed column readout circuit is introduced. The novel pixel readout, A/D conversion, and digital data transfer schemes are introduced to realize the readout rate and to reduce the interference noise. The 1 horizontal (1H) readout time is realized to be 1.0us.

Thanks to ND for the news!